JAJSNA7A November   2021  – February 2022 BQ27Z746

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
      1. 6.5.1 Supply Current
      2. 6.5.2 Common Analog (LDO, LFO, HFO, REF1, REF2, I-WAKE)
      3. 6.5.3 Battery Protection (CHG, DSG)
      4. 6.5.4 Cell Sensing Output (BAT_SP, BAT_SN)
      5. 6.5.5 Gauge Measurements (ADC, CC, Temperature)
      6. 6.5.6 Flash Memory
    6. 6.6 Digital I/O: DC Characteristics
    7. 6.7 Digital I/O: Timing Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  BQ27Z746 Processor
      2. 7.3.2  Battery Parameter Measurements
        1. 7.3.2.1 Coulomb Counter (CC) and Digital Filter
        2. 7.3.2.2 ADC Multiplexer
        3. 7.3.2.3 Analog-to-Digital Converter (ADC)
        4. 7.3.2.4 Internal Temperature Sensor
        5. 7.3.2.5 External Temperature Sensor Support
      3. 7.3.3  Power Supply Control
      4. 7.3.4  Bus Communication Interface
      5. 7.3.5  Low Frequency Oscillator
      6. 7.3.6  High Frequency Oscillator
      7. 7.3.7  1.8-V Low Dropout Regulator
      8. 7.3.8  Internal Voltage References
      9. 7.3.9  Overcurrent in Discharge Protection
      10. 7.3.10 Overcurrent in Charge Protection
      11. 7.3.11 Short-Circuit Current in Discharge Protection
      12. 7.3.12 Primary Protection Features
      13. 7.3.13 Battery Sensing
      14. 7.3.14 Gas Gauging
      15. 7.3.15 Zero Volt Charging (ZVCHG)
      16. 7.3.16 Charge Control Features
      17. 7.3.17 Authentication
    4. 7.4 Device Functional Modes
      1. 7.4.1 Lifetime Logging Features
      2. 7.4.2 Configuration
        1. 7.4.2.1 Coulomb Counting
        2. 7.4.2.2 Cell Voltage Measurements
        3. 7.4.2.3 Auto Calibration
        4. 7.4.2.4 Temperature Measurements
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements (Default)
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Changing Design Parameters
      3. 8.2.3 Calibration Process
      4. 8.2.4 Gauging Data Updates
        1. 8.2.4.1 Application Curve
  9. 9 Power Supply Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Orderable, and Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 Digital I/O: Timing Characteristics

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
I2C Timing — 100 kHz
fSCL Clock Operating Frequency SCL duty cycle = 50% 100 kHz
tHD:STA START Condition Hold Time 4.0 µs
tLOW Low period of the SCL Clock 4.7 µs
tHIGH High period of the SCL Clock 4.0 µs
tSU:STA Setup repeated START 4.7 µs
tHD:DAT Data hold time (SDA input) 0 ns
tSU:DAT Data setup time (SDA input) 250 ns
tr Clock Rise Time 10% to 90% 1000 ns
tf Clock Fall Time 90% to 10% 300 ns
tSU:STO Setup time STOP Condition 4.0 µs
tBUF Bus free time STOP to START 4.7 µs
I2C Timing — 400 kHz
fSCL Clock Operating Frequency SCL duty cycle = 50% 400 kHz
tHD:STA START Condition Hold Time 0.6 µs
tLOW Low period of the SCL Clock 1.3 µs
tHIGH High period of the SCL Clock 600 ns
tSU:STA Setup repeated START 600 ns
tHD:DAT Data hold time (SDA input) 0 ns
tSU:DAT Data setup time (SDA input) 100 ns
tr Clock Rise Time 10% to 90% 300 ns
tf Clock Fall Time 90% to 10% 300 ns
tSU:STO Setup time STOP Condition 0.6 µs
tBUF Bus free time STOP to START 1.3 µs
HDQ Timing
tB Break Time 190 µs
tBR Break Recovery Time 40 µs
tHW1 Host Write 1 Time Host drives HDQ 0.5 50 µs
tHW0 Host Write 0 Time Host drives HDQ 86 145 µs
tCYCH Cycle Time, Host to device device drives HDQ 190 µs
tCYCD Cycle Time, device to Host device drives HDQ 190 205 250 µs
tDW1 Device Write 1 Time device drives HDQ 32 50 µs
tDW0 Device Write 0 Time device drives HDQ 80 145 µs
tRSPS Device Response Time device drives HDQ 190 950 µs
tTRND Host Turn Around Time Host drives HDQ after device drives HDQ 250 µs
tRISE HDQ Line Rising Time to Logic 1 1.8 µs
tRST HDQ Reset Host drives HDQ low before device reset 2.2 s
GUID-84DD0DBB-0C69-4BA8-8F76-D9C5F8223F32-low.gif Figure 6-1 I2C Timing
GUID-3A2F0A25-05BB-490B-A0EF-F03CBB0C5379-low.gif Figure 6-2 HDQ Timing