JAJSII1B January   2020  – January 2022 BQ28Z610-R1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current
    6. 7.6  Power Supply Control
    7. 7.7  Low-Voltage General Purpose I/O, TS1
    8. 7.8  Power-On Reset (POR)
    9. 7.9  Internal 1.8-V LDO
    10. 7.10 Current Wake Comparator
    11. 7.11 Coulomb Counter
    12. 7.12 ADC Digital Filter
    13. 7.13 ADC Multiplexer
    14. 7.14 Cell Balancing Support
    15. 7.15 Internal Temperature Sensor
    16. 7.16 NTC Thermistor Measurement Support
    17. 7.17 High-Frequency Oscillator
    18. 7.18 Low-Frequency Oscillator
    19. 7.19 Voltage Reference 1
    20. 7.20 Voltage Reference 2
    21. 7.21 Instruction Flash
    22. 7.22 Data Flash
    23. 7.23 Current Protection Thresholds
    24. 7.24 Current Protection Timing
    25. 7.25 N-CH FET Drive (CHG, DSG)
    26. 7.26 I2C Interface I/O
    27. 7.27 I2C Interface Timing
    28. 7.28 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Battery Parameter Measurements
        1. 8.3.1.1 BQ28Z610-R1 Processor
      2. 8.3.2  Coulomb Counter (CC)
      3. 8.3.3  CC Digital Filter
      4. 8.3.4  ADC Multiplexer
      5. 8.3.5  Analog-to-Digital Converter (ADC)
      6. 8.3.6  ADC Digital Filter
      7. 8.3.7  Internal Temperature Sensor
      8. 8.3.8  External Temperature Sensor Support
      9. 8.3.9  Power Supply Control
      10. 8.3.10 Power-On Reset
      11. 8.3.11 Bus Communication Interface
      12. 8.3.12 I2C Timeout
      13. 8.3.13 Cell Balancing Support
      14. 8.3.14 N-Channel Protection FET Drive
      15. 8.3.15 Low Frequency Oscillator
      16. 8.3.16 High Frequency Oscillator
      17. 8.3.17 1.8-V Low Dropout Regulator
      18. 8.3.18 Internal Voltage References
      19. 8.3.19 Overcurrent in Discharge Protection
      20. 8.3.20 Short-Circuit Current in Charge Protection
      21. 8.3.21 Short-Circuit Current in Discharge 1 and 2 Protection
      22. 8.3.22 Primary Protection Features
      23. 8.3.23 Gas Gauging
      24. 8.3.24 Charge Control Features
      25. 8.3.25 Authentication
    4. 8.4 Device Functional Modes
      1. 8.4.1 Lifetime Logging Features
      2. 8.4.2 Configuration
        1. 8.4.2.1 Coulomb Counting
        2. 8.4.2.2 Cell Voltage Measurements
        3. 8.4.2.3 Current Measurements
        4. 8.4.2.4 Auto Calibration
        5. 8.4.2.5 Temperature Measurements
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements (Default)
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Setting Design Parameters
        2. 9.2.2.2 Calibration Process
        3. 9.2.2.3 Gauging Data Updates
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.25 N-CH FET Drive (CHG, DSG)

Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 7.6 V (unless otherwise noted)
PARAMETERTEST CONDITIONMINTYPMAXUNIT
Output voltage ratioRatioDSG = (VDSG – VVC2)/VVC2, 2.2 V < VVC2 < 4.07 V, 10 MΩ between PACK and DSG2.1332.3332.467—
RatioCHG = (VCHG – VVC2)/VVC2, 2.2 V < VVC2 < 4.07 V, 10 MΩ between BAT and CHG2.1332.3332.467
V(FETON)Output voltage, CHG and DSG onVDSG(ON) = VDSG – VVC2, 4.07 V ≤ VVC2 ≤ 18 V, 10 MΩ between PACK and DSG8.759.510.25V
VCHG(ON) = VCHG – VVC2, 4.07 V ≤ VVC2 ≤ 18 V, 10 MΩ between VC2 and CHG8.759.510.25
V(FETOFF)Output voltage, CHG and DSG offVDSG(OFF) = VDSG – VPACK, 10 MΩ between PACK and DSG–0.40.4V
VCHG(OFF) = VCHG – VBAT, 10 MΩ between VC2 and CHG–0.40.4
tRRise timeVDSG from 0% to 35% VDSG(ON)(TYP), VBAT ≥ 2.2 V, CL = 4.7 nF between DSG and PACK, 5.1 kΩ between DSG and CL, 10 MΩ between PACK and DSG200500µs
VCHG from 0% to 35% VCHG(ON)(TYP), VVC2 ≥ 2.2 V, CL = 4.7 nF between CHG and VC2, 5.1 kΩ between CHG and CL, 10 MΩ between VC2 and CHG200500
tFFall timeVDSG from VDSG(ON)(TYP) to 1 V, VVC2 ≥ 2.2 V, CL = 4.7 nF between DSG and PACK, 5.1 kΩ between DSG and CL, 10 MΩ between PACK and DSG40300µs
VCHG from VCHG(ON)(TYP) to 1 V, VVC2 ≥ 2.2 V, CL = 4.7 nF between CHG and VC2, 5.1 kΩ between CHG and CL, 10 MΩ between VC2 and CHG40200