JAJSM57D april   2014  – june 2021 BQ28Z610

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Description (Continued)
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current
    6. 7.6  Power Supply Control
    7. 7.7  Low-Voltage General Purpose I/O, TS1
    8. 7.8  Power-On Reset (POR)
    9. 7.9  Internal 1.8-V LDO
    10. 7.10 Current Wake Comparator
    11. 7.11 Coulomb Counter
    12. 7.12 ADC Digital Filter
    13. 7.13 ADC Multiplexer
    14. 7.14 Cell Balancing Support
    15. 7.15 Internal Temperature Sensor
    16. 7.16 NTC Thermistor Measurement Support
    17. 7.17 High-Frequency Oscillator
    18. 7.18 Low-Frequency Oscillator
    19. 7.19 Voltage Reference 1
    20. 7.20 Voltage Reference 2
    21. 7.21 Instruction Flash
    22. 7.22 Data Flash
    23. 7.23 Current Protection Thresholds
    24. 7.24 Current Protection Timing
    25. 7.25 N-CH FET Drive (CHG, DSG)
    26. 7.26 I2C Interface I/O
    27. 7.27 I2C Interface Timing
    28. 7.28 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Battery Parameter Measurements
        1. 8.3.1.1 BQ28Z610 Processor
      2. 8.3.2  Coulomb Counter (CC)
      3. 8.3.3  CC Digital Filter
      4. 8.3.4  ADC Multiplexer
      5. 8.3.5  Analog-to-Digital Converter (ADC)
      6. 8.3.6  ADC Digital Filter
      7. 8.3.7  Internal Temperature Sensor
      8. 8.3.8  External Temperature Sensor Support
      9. 8.3.9  Power Supply Control
      10. 8.3.10 Power-On Reset
      11. 8.3.11 Bus Communication Interface
      12. 8.3.12 Cell Balancing Support
      13. 8.3.13 N-Channel Protection FET Drive
      14. 8.3.14 Low Frequency Oscillator
      15. 8.3.15 High Frequency Oscillator
      16. 8.3.16 1.8-V Low Dropout Regulator
      17. 8.3.17 Internal Voltage References
      18. 8.3.18 Overcurrent in Discharge Protection
      19. 8.3.19 Short-Circuit Current in Charge Protection
      20. 8.3.20 Short-Circuit Current in Discharge 1 and 2 Protection
      21. 8.3.21 Primary Protection Features
      22. 8.3.22 Gas Gauging
      23. 8.3.23 Charge Control Features
      24. 8.3.24 Authentication
    4. 8.4 Device Functional Modes
      1. 8.4.1 Lifetime Logging Features
      2. 8.4.2 Configuration
        1. 8.4.2.1 Coulomb Counting
        2. 8.4.2.2 Cell Voltage Measurements
        3. 8.4.2.3 Current Measurements
        4. 8.4.2.4 Auto Calibration
        5. 8.4.2.5 Temperature Measurements
  10. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements (Default)
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Setting Design Parameters
      3. 9.2.3 Calibration Process
      4. 9.2.4 Gauging Data Updates
        1. 9.2.4.1 Application Curve
  11.   Power Supply Requirements
  12. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  13. 11Device and Documentation Support
    1. 11.1 サード・パーティ製品に関する免責事項
    2. 11.2 Documentation Support
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 用語集
  14.   Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.11 Bus Communication Interface

The BQ28Z610 device has an I2C bus communication interface. This device has the option to broadcast information to a smart charger to provide key information to adjust the charging current and charging voltage based on the temperature or individual cell voltages.

CAUTION:

If the device is configured as a single-master architecture (an application processor) and an occasional NACK is detected in the operation, the master can resend the transaction. However, in a multi-master architecture, an incorrect ACK leading to accidental loss of bus arbitration can cause a master to wait incorrectly for another master to clear the bus. If this master does not get a bus-free signal, then it must have in place a method to look for the bus and assume it is free after some period of time. Also, if possible, set the clock speed to be 100 kHz or less to significantly reduce the issue described above for multi-mode operation.