SLUSA52C September   2010  – March 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Recommended Cell Balancing Configurations
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Voltage Protection
      2. 8.1.2 Cell Balancing
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Protection (OUT) Timing
      2. 8.3.2 Cell Voltage > VPROTECT
      3. 8.3.3 Cell Connection Sequence
      4. 8.3.4 Cell Balance Enable Control
      5. 8.3.5 Cell Balance Configuration
      6. 8.3.6 Cell Imbalance Auto-Detection (Via Cell Voltage)
      7. 8.3.7 Customer Test Mode
      8. 8.3.8 Test Conditions
    4. 8.4 Device Functional Modes
      1. 8.4.1 NORMAL Mode
      2. 8.4.2 PROTECTION Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Battery Connection
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
    3. 9.3 System Example
      1. 9.3.1 External Cell Balancing
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DRB|8
サーマルパッド・メカニカル・データ
発注情報

4 Revision History

Changes from B Revision (December 2014) to C Revision

  • Changed Typical Application title to Simplified Schematic Go
  • Changed resistor RVD location, added PACK+ and PACK- in the Simplified Schematic imageGo
  • Deleted the Lead Temperature (soldering) from the Absolute Maximum Ratings table Go
  • Deleted table notes 2 through 7 from the Thermal InformationGo
  • Changed resistor RVD location in Figure 9 Go
  • Added title to Table 1Go
  • Changed resistor RVD location, added PACK+ and PACK- in Figure 11 Go

Changes from A Revision (September 2010) to B Revision

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo

Changes from * Revision (June 2010) to A Revision

  • Changed values in XDELAY and XDELAY_CTM electrical characteristicsGo
  • Changed specifications for VOUTGo
  • Changed test conditions for VOUT, IOH, and IOLGo
  • Added VMM_DET_ON: VC2 = VDD = 7.6 VGo
  • Changed VMM_DET_OFF: From VDD – VC2 – 7.6 V to VC2 = VDD = 7.6 VGo
  • Changed content in Recommended Cell Balancing Configurations sectionGo
  • Added ICD Charge Current figureGo
  • Added ICD Discharge Current figureGo
  • Changed XDELAY from nominally 8.0 s/µF to nominally 9.0 s/µFGo
  • Changed Timing for Overvoltage Sensing figureGo
  • Added Cell Imbalance Auto-Detection (Via Cell Voltage) sectionGo
  • Changed VDD value in Customer Test Mode from 8.5 V to 9.5 VGo
  • Changed the Voltage Test Limits figureGo
  • Added External Cell Balancing sectionGo