JAJSFJ5I March   2014  – August 2024 BQ2970 , BQ2971 , BQ2972 , BQ2973

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Descriptions
      1. 5.1.1 Supply Input: BAT
      2. 5.1.2 Cell Negative Connection: VSS
      3. 5.1.3 Voltage Sense Node: V–
      4. 5.1.4 Discharge FET Gate Drive Output: DOUT
      5. 5.1.5 Charge FET Gate Drive Output: COUT
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Characteristics
    6. 6.6 Programmable Fault Detection Thresholds
    7. 6.7 Programmable Fault Detection Timer Ranges
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Timing Charts
    2. 7.2 Test Circuits
    3. 7.3 Test Circuit Diagrams
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 Overcharge Status
      3. 8.4.3 Over-Discharge Status
      4. 8.4.4 Discharge Overcurrent Status (Discharge Overcurrent, Load Short-Circuit)
      5. 8.4.5 Charge Overcurrent Status
      6. 8.4.6 0V Charging Function Enabled
      7. 8.4.7 0V Charging Inhibit Function
      8. 8.4.8 Delay Circuit
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Performance Plots
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Related Documentation
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2 Detailed Design Procedure

Note:

The external FET selection is important to ensure the battery pack protection is sufficient and complies to the requirements of the system.

  • FET Selection: Because the maximum desired discharge current is 7A, ensure that the Discharge Overcurrent circuit does not trigger until the discharge current is above this value.
  • The total resistance tolerated across the two external FETs (CHG + DSG) should be 100mV/7A = 14.3mΩ.
  • Based on the information of the total ON resistance of the two switches, determine what would be the Charge Overcurrent Detection threshold, 14.3mΩ × 4.5A = 65mV. Selecting a device with a 70mV trigger threshold for Charge Overcurrent trigger is acceptable.
  • The total Rds ON should factor in any worst-case parameter based on the FET ON resistance, derating due to temperature effects and minimum required operation, and the associated gate drive (Vgs). Therefore, the FET choice should meet the following criteria:

        Vdss = 25V

        Each FET Rds ON = 7.5mΩ at Tj = 25°C and Vgs = 3.5V

  • Imax > 50A to allow for short Circuit Current condition for 350µs (max delay timer). The only limiting factor during this condition is Pack Voltage/(Cell Resistance + (2 × FET_RdsON) + Trace Resistance).
  • Use the CSD16406Q3 FET for the application.
  • An RC filter is required on the BAT for noise, and enables the device to operate during sharp negative transients. The 330Ω resistor also limits the current during a reverse connection on the system.
  • TI recommends placing a high impedance 5MΩ across the gate source of each external FET to deplete any charge on the gate-source capacitance.