SLUSA92D January   2011  – May 2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current
    6. 7.6  Power-On Reset (POR)
    7. 7.7  WAKE FROM SLEEP
    8. 7.8  RBI RAM Backup
    9. 7.9  3.3-V Regulator
    10. 7.10 2.5-V Regulator
    11. 7.11 DISP, PRES, SMBD, SMBC
    12. 7.12 CHG, DSG FET Drive
    13. 7.13 Internal Precharge Limiting
    14. 7.14 GPOD
    15. 7.15 FUSE
    16. 7.16 LED5, LED4, LED3, LED2, LED1
    17. 7.17 Coulomb Counter
    18. 7.18 VC1, VC2, VC3, VC4
    19. 7.19 TS1, TS2
    20. 7.20 Internal Temperature Sensor
    21. 7.21 Internal Thermal Shutdown
    22. 7.22 High Frequency Oscillator
    23. 7.23 Low Frequency Oscillator
    24. 7.24 Internal Voltage Reference
    25. 7.25 Flash
    26. 7.26 OCD Current Protection
    27. 7.27 SCD1 Current Protection
    28. 7.28 SCD2 Current Protection
    29. 7.29 SCC Current Protection
    30. 7.30 SBS Timing Requirements
    31. 7.31 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Primary (1st Level) Safety Features
      2. 8.3.2 Secondary (2nd Level) Safety Features
      3. 8.3.3 Charge Control Features
      4. 8.3.4 Gas Gauging
      5. 8.3.5 Lifetime Data Logging Features
      6. 8.3.6 Authentication
    4. 8.4 Device Functional Modes
    5. 8.5 Configuration
      1. 8.5.1 Oscillator Function
      2. 8.5.2 System Present Operation
      3. 8.5.3 2-, 3-, or 4-Cell Configuration
      4. 8.5.4 Cell Balancing
        1. 8.5.4.1 Internal Cell Balancing
        2. 8.5.4.2 External Cell Balancing
    6. 8.6 Battery Parameter Measurements
      1. 8.6.1 Charge and Discharge Counting
      2. 8.6.2 Voltage
      3. 8.6.3 Current
      4. 8.6.4 Auto Calibration
      5. 8.6.5 Temperature
      6. 8.6.6 Communications
        1. 8.6.6.1 SMBus On and Off State
        2. 8.6.6.2 SBS Commands
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 High-Current Path
          1. 9.2.2.1.1 Protection FETs
          2. 9.2.2.1.2 Chemical Fuse
          3. 9.2.2.1.3 Lithium-Ion Cell Connections
          4. 9.2.2.1.4 Sense Resistor
          5. 9.2.2.1.5 ESD Mitigation
        2. 9.2.2.2 Gas Gauge Circuit
          1. 9.2.2.2.1 Differential Low-Pass Filter
          2. 9.2.2.2.2 Power Supply Decoupling and RBI
          3. 9.2.2.2.3 System Present
          4. 9.2.2.2.4 SMBus Communication
          5. 9.2.2.2.5 FUSE Circuitry
          6. 9.2.2.2.6 PFIN Detection
        3. 9.2.2.3 Secondary-Current Protection
          1. 9.2.2.3.1 Cell and Battery Inputs
          2. 9.2.2.3.2 External Cell Balancing
          3. 9.2.2.3.3 PACK and FET Control
          4. 9.2.2.3.4 Regulator Output
          5. 9.2.2.3.5 Temperature Output
          6. 9.2.2.3.6 LEDs
          7. 9.2.2.3.7 Safety PTC Thermistor
        4. 9.2.2.4 Secondary-Overvoltage Protection
          1. 9.2.2.4.1 Cell Inputs
          2. 9.2.2.4.2 Time-Delay Capacitor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

bq3050 Pin_Out_bq3050.gif

Pin Functions

PIN NAME PIN NUMBER TYPE(1) DESCRIPTION
CHG 1 O Charge N-FET gate drive
PCR 2 O Internal Precharge FET output
BAT 3 P Alternate power source
VC1 4 I Sense input for positive voltage of top most cell in stack and cell balancing input for top most cell in stack
VC2 5 I Sense input for positive voltage of third lowest cell in stack and cell balancing input for third lowest cell in stack
VC3 6 I Sense input for positive voltage of second lowest cell in stack and cell balancing input for second lowest cell in stack
VC4 7 I Sense input for positive voltage of lowest cell in stack and cell balancing input for lowest cell in stack
VSS 8 P Device ground
VSS 9 P Device ground
TS1 10 AI Temperature sensor 1 thermistor input
SRP 11 AI Differential Coulomb Counter input
NC 12 — Not internally connected. Connect to VSS.
SRN 13 AI Differential Coulomb Counter input
NC 14 — Not internally connected. Connect to VSS.
TS2 15 AI Temperature sensor 2 thermistor input
PRES 16 I Host system present input
SMBD 17 I/OD SMBus v1.1 data line
NC 18 — Not internally connected. Connect to VSS.
SMBC 19 I/OD SMBus v1.1 clock line
DISP 20 I Display active input
NC 21 — Not internally connected. Connect to VSS.
LED5 22 O LED display constant current sink
LED4 23 O LED display constant current sink
LED3 24 O LED display constant current sink
LED2 25 O LED display constant current sink
LED1 26 O LED display constant current sink
RBI 27 P RAM backup
REG25 28 P 2.5-V regulator output
VSS 29 P Device ground
VSS 30 P Device ground
REG33 31 P 3.3-V regulator output
TEST 32 — Test pin, connect to VSS through 10-kΩ resistor
FUSE 33 O Fuse drive
PCHGIN 34 I Internal Precharge FET input
VCC 35 P Power supply voltage
GPOD 36 I/OD High voltage general purpose I/O
PACK 37 P Alternate power source
DSG 38 O Discharge N-FET gate drive
(1) P = Power Connection, O = Digital Output, AI = Analog Input, I = Digital Input, I/OD = Digital Input/Output