SLUS928B March   2009  – July 2016

 

  1. 1Features
  2. 2Applications
  3. 3Description
    1.     Device Images
      1.      System Partitioning Diagram
  4. 4Revision History
  5. 5Pin Configuration and Functions
    1.     Pin Functions
  6. 6Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  7. 7Detailed Description
    1. 7.1 Feature Description
      1. 7.1.1  Battery Parameter Measurements
        1. 7.1.1.1 Charge and Discharge Counting
        2. 7.1.1.2 Voltage
        3. 7.1.1.3 Voltage Calibration and Accuracy
        4. 7.1.1.4 Current
        5. 7.1.1.5 Auto Calibration
        6. 7.1.1.6 Temperature
      2. 7.1.2  Primary (1st Level) Safety Features
      3. 7.1.3  Secondary (2nd Level) Safety Features
      4. 7.1.4  Charge Control Features
      5. 7.1.5  Gas Gauging
      6. 7.1.6  Lifetime Data Logging Features
      7. 7.1.7  Authentication
      8. 7.1.8  Configuration
        1. 7.1.8.1 System Present Operation
        2. 7.1.8.2 2-, 3-, or 4-Cell Configuration
        3. 7.1.8.3 Cell Balance Control
      9. 7.1.9  Communications
        1. 7.1.9.1 SMBus On and Off State
      10. 7.1.10 SBS Commands
    2. 7.2 Device Functional Modes
      1. 7.2.1 Power Modes
  8. 8Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Community Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

PW Package
24-Pin TSSOP
Top View
bq3060 po_lus928.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
BAT 1 P Power input from battery
DSG 2 O P-CH FET Drive controlling discharge
VC1 3 IA Sense voltage input terminal and external cell balancing drive output for most positive cell, and battery stack measurement input.
VC2 4 IA Sense voltage input terminal and external cell balancing drive output for second most positive cell.
VC3 5 IA Sense voltage input terminal and external cell balancing drive output for third most positive cell.
VC4 6 IA Sense voltage input terminal and external cell balancing drive output for least positive cell.
SRP 7 IA Analog input pin connected to the internal coulomb-counter peripheral for integrating a small voltage between SRP and SRN where SRP is the top of the sense resistor.
SRN 8 IA Analog input pin connected to the internal coulomb-counter peripheral for integrating a small voltage between SRP and SRN where SRN is the bottom of the sense resistor.
TS1 9 I/O,IA Thermistor input TS1
TS2 10 I/O,IA Thermistor input TS2
NC 11 — Keep this pin floating
NC 12 — Keep this pin floating
NC 13 — Keep this pin floating
SMBD 14 I/OD SMBus data pin
NC 15 — Keep this pin floating
SMBC 16 I/OD SMBus clock pin
PRES 17 I/OD Active low input to sense system insertion and typically requires additional ESD protection
RBI 18 P RAM backup pin to provide backup potential to the internal DATA RAM if power is momentarily lost by using a capacitor attached between RBI and VSS
VSS 19 P Device ground
REG27 20 P Internal power supply 2.7V bias output
FUSE 21 I/OD Push-pull fuse drive and secondary protector activation input sensing
ZVCHG 22 O P-CH precharge FET Drive controlling pre-charge and zero-volt charge
CHG 23 O P-CH FET Drive controlling charge
PACK 24 P PACK positive terminal and alternative power source