The Texas Instruments BQ33100 Super Capacitor Manager is a fully integrated, single-chip solution that provides a rich array of features for charge control, monitoring, and protection for either 2-, 3-, 4-, or 5-series super capacitors with individual capacitor monitoring and balancing or up to 9-series capacitors with only the stack voltage being measured. With a small footprint of 7.8 mm × 6.4 mm in a compact 24-pin TSSOP package, the BQ33100 maximizes functionality and safety while dramatically increasing ease of use and cutting the solution cost and size for super capacitor applications.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
BQ33100 | TSSOP (24) | 7.80 mm × 4.40 mm |
Changes from B Revision (December 2015) to C Revision
Changes from A Revision (March 2011) to B Revision
Changes from * Revision (January 2011) to A Revision
Using its integrated high-performance analog peripherals, the BQ33100 battery manager measures and maintains an accurate record of available capacitance, state-of-health, voltage, current, temperature, and other critical parameters in super capacitors, and reports the information to the system host controller over a 2-wire SMBus 1.1 compatible interface.
The BQ33100 provides firmware-controlled protection on overvoltage, overtemperature, and overcharge, along with hardware-controlled protection for overcurrent in discharge and short circuit protection during charge and discharge.
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
CHG | 23 | O | P-Channel FET drive for controlling charge |
CHGLVL0 | 11 | O | Charge Control Output 0 |
CHGLVL1 | 12 | O | Charge Control Output 1 |
CHGOR | 21 | I | CHG override input. If not used, connect to VSS. |
FAULT | 15 | O | Active high output to indicate fault condition |
GND | 19 | P | Ground |
LLEN | 17 | O | Learn Load Enable Output |
NC | 2 | O | Not used and must be connected to VCC |
NC | 22 | — | No connect. Leave the NC pin floating. |
RBI | 18 | P | RAM backup pin to provide backup potential to the internal DATA RAM if power is momentarily lost by using a capacitor attached between RBI and GND. |
REG27 | 20 | P | Internal power supply 2.7-V bias output |
SCL | 16 | I/OD | Serial clock input: Clocks data on SDA |
SDA | 14 | I/OD | Serial data: transmits and receives data |
SRN | 8 | IA | Analog input pin connected to the internal ADC peripheral for measuring a small voltage between SRP and SRN where SRN is the bottom of the sense resistor. |
SRP | 7 | IA | Analog input pin connected to the internal ADC peripheral for measuring a small voltage between SRP and SRN where SRP is the top of the sense resistor. |
TS | 9 | IA | Thermistor input |
VC1 | 3 | IA | Sense voltage input terminal and external capacitor voltage balancing drive output for the 5th-series capacitor, and stack measurement input. See Series Capacitor Configuration for systems with less than 5 series. |
VC2 | 4 | IA | Sense voltage input terminal and external capacitor voltage balancing drive output for the 4th-series capacitor. See Series Capacitor Configuration for systems with less than 5 series. |
VC3 | 5 | IA | Sense voltage input terminal and external capacitor voltage balancing drive output for the 3rd-series capacitor. See Series Capacitor Configuration for systems with less than 5 series. |
VC4 | 6 | IA | Sense voltage input terminal and external capacitor voltage balancing drive output for the 2nd-series capacitor. See Series Capacitor Configuration for systems with less than 5 series. |
VC5 | 10 | IA | Sense voltage input terminal and external capacitor voltage balancing drive output for the 1st capacitor. See Series Capacitor Configuration for systems with less than 5 series. |
VC5BAL | 13 | O | Cell balance control output for the least positive capacitor (only used in a 5-series capacitor configuration) |
VCCPACK | 1 | P | Power supply from the super capacitors. The top of the super capacitor stack must be connected to this pin. |
VCC | 24 | P | Positive input from power supply |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VMAX | Supply voltage | VCC w.r.t. GND | –0.3 | 34 | V |
VIN | Input voltage | VC1, VCC | VVC2 – 0.3 | VVC2 + 8.5 or 34, whichever is lower | V |
VC2 | VVC3 – 0.3 | VVC3 + 8.5 | V | ||
VC3 | VVC4 – 0.3 | VVC4 + 8.5 | V | ||
VC4 | VSRP – 0.3 | VSRP + 8.5 | V | ||
SRP, SRN | –0.3 | VREG27 | V | ||
SDA, SCL | –0.3 | 6.0 | V | ||
CHGOR | –0.3 | VCC | V | ||
TS, VC5, CHGLVL0, CHGLVL1, FAULT | –0.3 | VREG27 + 0.3 | V | ||
VO | Output voltage | CHG | –0.3 | VCC | V |
VC5BAL | –0.3 | VREG27 + 0.3 | V | ||
RBI, REG27 | –0.3 | 2.75 | V | ||
ISS | Maximum combined sink current for input pins | 50 | mA | ||
TFUNC | Functional temperature | –40 | 110 | °C | |
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
THERMAL METRIC(1) | BQ33100 | UNIT | |
---|---|---|---|
PW (TSSOP) | |||
24 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 83.6 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 16.5 | °C/W |
RθJB | Junction-to-board thermal resistance | 39.4 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.4 | °C/W |
ψJB | Junction-to-board characterization parameter | 38.8 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | — | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VIH | High-level input voltage | SDA, SCL, TS, VC5 | 2 | V | |||
VIL | Low-level input voltage | SDA, SCL, TS, VC5 | 0.8 | V | |||
VOH | Output voltage high | SDA, SCL, VC5BAL, CHGLVL0, CHGLVL1, LLEN, FAULT, IL = –0.5 mA | VREG27 – 0.5 | V | |||
VOL | Low-level output voltage | SDA, SCL, VC5BAL, CHGLVL0, CHGLVL1, LLEN, FAULT, IL = 7 mA | 0.4 | V | |||
CIN | Input capacitance | 5 | pF | ||||
Ilkg | Input leakage current | SDA, SCL, TS, VC5, CHGLVL0, CHGLVL1, LLEN, FAULT
SDA and SCL pulldown disabled |
1 | µA | |||
VCHGOR | CHG override active high | 0.8 | 2 | 3.2 | V | ||
RPD(SMBx) | SDA and SCL pulldown | TA = –40°C to 100°C | 600 | 950 | 1300 | kΩ | |
RPAD | Pad resistance | TS | 87 | 110 | Ω |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ICC | NORMAL mode | Firmware running, no flash writes | 660 | µA | ||
ISHUTDOWN | SHUTDOWN mode | TA = –40°C to 110°C | 0.5 | 1 | µA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VREG– | Regulator output voltage | IREG27 = 10 mA | TA = –40°C to 85°C | 2.5 | 2.7 | 2.75 | V |
VREG27IT– | Negative-going POR voltage | At REG27 | 2.22 | 2.35 | 2.34 | V | |
VREG27IT+ | Positive-going POR voltage | At REG27 | 2.25 | 2.5 | 2.6 | V | |
ΔV(REGTEMP) | Regulator output change with temperature | IREG = 10 mA | TA = –40°C to 85°C | ±0.5% | |||
ΔV(REGLINE) | Line regulation | IREG = 10 mA | ±2 | ±4 | mV | ||
ΔV(REGLOAD) | Load regulation | IREG = 0.2 to 10 mA | ±20 | ±40 | mV | ||
I(REGMAX) | Current limit | 25 | 50 | mA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Input voltage range | –0.2 | 0.25 | V | ||
Conversion time | Single conversion | 250 | ms | ||
Effective resolution | Single conversion | 15 | Bits | ||
Integral nonlinearity | TA = –25°C to 85°C | ±0.007% | ±0.034% | FSR | |
Offset error(1) | TA = –25°C to 85°C | 10 | µV | ||
Offset error drift | 0.3 | 0.5 | µV/°C | ||
Full-scale error(2) | –0.8% | 0.2% | 0.8% | ||
Full-scale error drift | 150 | PPM/°C | |||
Effective input resistance | 2.5 | MΩ |
PARAMETER | TEST CONDITION | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Input voltage range | TS, VC5 | –0.2 | 0.8 × VREG27 | V | |
Conversion time | 31.5 | ms | |||
Resolution (no missing codes) | 16 | Bits | |||
Effective resolution | 14 | 15 | Bits | ||
Integral nonlinearity | ±0.02% | FSR | |||
Offset error(1) | 70 | 160 | µV | ||
Offset error drift | 1 | µV/°C | |||
Full-scale error | VIN = 1 V | –0.8% | ±0.2% | 0.4% | |
Full-scale error drift | 150 | PPM/°C | |||
Effective input resistance | 8 | MΩ |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
RBAL_drive | Internal pulldown resistance for external capacitor voltage balance | Capacitor voltage balance ON for VC1,
VCi – VCi + 1 = 4 V, where i = 1 to approximately 4 |
5.7 | kΩ | ||
Capacitor voltage balance ON for VC2,
VCi – VCi + 1 = 4 V, where = i = 1 to approximately 4 |
3.7 | |||||
Capacitor voltage balance ON for VC3,
VCi – VCi + 1 = 4 V, where = i = 1 to approximately 4 |
1.75 | |||||
Capacitor voltage balance ON for VC4,
VCi – VCi + 1 = 4 V, where = i = 1 to approximately 4 |
0.85 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
CAPACITOR Voltage Measurement Accuracy | TA = –10°C to 60°C | ±10 | ±20 | mV | ||
TA = –40°C to 85°C | ±10 | ±35 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
T(TEMP) | Temperature sensor accuracy | ±3% | °C |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
RERR | Internal resistor drift | –230 | ppm/°C | |||
R | Internal resistor | TS | 17 | 20 | kΩ |
PARAMETER(1) | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
TMAX | Maximum REG27 temperature | 125 | 175 | °C | ||
TRECOVER | Recovery hysteresis temperature | 10 | °C |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
f(OSC) | Operating frequency of CPU clock | 2.097 | MHz | |||
f(EIO) | Frequency error(1) | TA = –20°C to 70°C | –2% | ±0.25% | 2% | |
TA = –40°C to 85°C | –3% | ±0.25% | 3% | |||
t(SXO) | Start-up time(2) | TA = –25°C to 85°C | 3 | 6 | ms |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
f(LOSC) | Operating frequency | 32.768 | MHz | |||
f(LEIO) | Frequency error(1) | TA = –20°C to 70°C | –1.5% | ±0.25% | 1.5% | |
TA = –40°C to 85°C | –2.5% | ±0.25% | 2.5% | |||
t(LSXO) | Start-up time(2) | TA = –25°C to 85°C | 100 | ms |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
I(RBI) | RBI data-retention input current | VRBI > V(RBI)MIN, VREG27 < VREG27IT-,
TA = 70°C to 110°C |
20 | 1500 | nA | |
VRBI > V(RBI)MIN, VREG27 < VREG27IT-,
TA = –40°C to 70°C |
500 | |||||
V(RBI) | RBI data-retention voltage(1) | 1 | V |
PARAMETER(1) | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Data retention | 10 | Years | ||||
Flash programming write-cycles | 20k | Cycles | ||||
t(ROWPROG) | Row programming time | 2 | ms | |||
t(MASSERASE) | Mass-erase time | 250 | ms | |||
t(PAGEERASE) | Page-erase time | 25 | ms | |||
ICC(PROG) | Flash-write supply current | 4 | 6 | mA | ||
ICC(ERASE) | Flash-erase supply current | TA = –40°C to 0°C | 8 | 22 | mA | |
TA = 0°C to 85°C | 3 | 15 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
V(OCD) | OCD detection threshold voltage range, typical | RSNS = 0 | RSNS is set in STATE_CTL register | 50 | 200 | mV | |
RSNS = 1 | 25 | 100 | |||||
ΔV(OCDT) | OCD detection threshold voltage program step | RSNS = 0 | 10 | mV | |||
RSNS = 1 | 5 | ||||||
V(SCCT) | SCC detection threshold voltage range, typical | RSNS = 0 | –100 | –300 | mV | ||
RSNS = 1 | –50 | –225 | |||||
ΔV(SCCT) | SCC detection threshold voltage program step | RSNS = 0 | –50 | mV | |||
RSNS = 1 | –25 | ||||||
V(SCDT) | SCD detection threshold voltage range, typical | RSNS = 0 | 100 | 450 | mV | ||
RSNS = 1 | 50 | 225 | |||||
ΔV(SCDT) | SCD detection threshold voltage program step | RSNS = 0 | 50 | mV | |||
RSNS = 1 | 25 | ||||||
V(OFFSET) | SCD, SCC and OCD offset | –10 | 10 | mV | |||
V(Scale_Err) | SCD, SCC and OCD scale error | –10% | 10% |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
t(OCDD) | Overcurrent in discharge delay | 1 | 31 | ms | ||
t(OCDD_STEP) | OCDD step options | 2 | ms | |||
t(SCDD) | Short circuit in discharge delay | AFE.STATE_CNTL[SCDDx2] = 0 | 0 | 915 | µs | |
AFE.STATE_CNTL[SCDDx2] = 1 | 0 | 1830 | ||||
t(SCDD_STEP) | SCDD step options | AFE.STATE_CNTL[SCDDx2] = 0 | 61 | µs | ||
AFE.STATE_CNTL[SCDDx2] = 1 | 122 | |||||
t(SCCD) | Short circuit in charge delay | 0 | 915 | µs | ||
t(SCCD_STEP) | SCCD step options | 61 | µs | |||
t(DETECT) | Current fault detect time | VSRP-SRN = VTHRESH + 12.5 mV,
TA = –40°C to 85°C |
35 | 160 | µs | |
tACC | Overcurrent and short circuit delay time accuracy | Accuracy of typical delay time with WDI active | –20% | 20% | ||
Accuracy of typical delay time with no WDI input | –50% | 50% |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
fSMB | SMBus operating frequency | Slave mode, SCL 50% duty cycle | 10 | 100 | kHz | |
fMAS | SMBus master clock frequency | Master mode, no clock low slave extend | 51.2 | kHz | ||
tBUF | Bus free time between start and stop | 4.7 | µs | |||
tHD:STA | Hold time after (repeated) start | 4 | µs | |||
tSU:STA | Repeated start setup time | 4.7 | µs | |||
tSU:STO | Stop setup time | 4 | µs | |||
tHD:DAT | Data hold time | Receive mode | 0 | ns | ||
Transmit mode | 300 | |||||
tSU:DAT | Data setup time | 250 | ns | |||
tTIMEOUT | Error signal and detect | See (1) | 25 | 35 | ms | |
tLOW | Clock low period | 4.7 | µs | |||
tHIGH | Clock high period | See (2) | 4 | 50 | µs | |
tLOW:SEXT | Cumulative clock low slave extend time | See (3) | 25 | ms | ||
tLOW:MEXT | Cumulative clock low master extend time | See (4) | 10 | ms | ||
tF | Clock and data fall time | See (5) | 300 | ns | ||
tR | Clock and data rise time | See (6) | 1000 | ns |