SLUSCI1B August   2016  – November 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Supply Current
    6. 6.6  Electrical Characteristics: Digital Input and Output DC Characteristics
    7. 6.7  Electrical Characteristics: Power-On Reset
    8. 6.8  Electrical Characteristics: LDO Regulator
    9. 6.9  Electrical Characteristics: Internal Temperature Sensor
    10. 6.10 Electrical Characteristics: Low-Frequency Clock Oscillator
    11. 6.11 Electrical Characteristics: High-Frequency Clock Oscillator
    12. 6.12 Electrical Characteristics: Integrating ADC (Coulomb Counter)
    13. 6.13 Electrical Characteristics: ADC (Temperature and Voltage Measurements)
    14. 6.14 Electrical Characteristics: Data Flash Memory
    15. 6.15 Timing Requirements: I2C-Compatible Interface Timing Characteristics
    16. 6.16 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Communications
        1. 7.3.1.1 I2C Interface
        2. 7.3.1.2 I2C Time Out
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 BAT Voltage Sense Input
        2. 8.2.2.2 SRP and SRN Current Sense Inputs
        3. 8.2.2.3 Sense Resistor Selection
        4. 8.2.2.4 TS Temperature Sense Input
        5. 8.2.2.5 Thermistor Selection
        6. 8.2.2.6 REGIN Power Supply Input Filtering
        7. 8.2.2.7 REG25 LDO Output Filtering
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Supply Decoupling Capacitor
      2. 10.1.2 Capacitors
      3. 10.1.3 Communication Line Protection Components
    2. 10.2 Layout Example
      1. 10.2.1 Ground System
      2. 10.2.2 Kelvin Connections
      3. 10.2.3 Board Offset Considerations
      4. 10.2.4 ESD Spark Gap
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VREGIN Regulator input range –0.3 5.5 V
VCE CE input pin –0.3 VREGIN + 0.3 V
VREG25 Supply voltage range –0.3 2.75 V
VIOD Open-drain I/O pins (SDA, SCL, ALERT2) –0.3 5.5 V
VBAT BAT input pin –0.3 5.5 V
VI Input voltage range to all other pins (SRP, SRN, TS, ALERT1, VEN/GPIO, LEN) –0.3 VREG25 + 0.3 V
TA Operating free-air temperature range –40 85 °C
TJ Operating junction temperature range –40 100 °C
TF Functional temperature range –40 100 °C
TSTG Storage temperature range –65 150 °C
Lead temperature (soldering, 10 s) –40 100 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, BAT pin(1) ±1500 V
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all other pins(1) ±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

TA= –40°C to 85°C, VREGIN = VBAT = 3.6 V (unless otherwise noted)
MIN NOM MAX UNIT
VREGIN Supply Voltage No operating restrictions 2.7 4.5 V
No FLASH writes 2.45 2.7 V
CREGIN External input capacitor for internal LDO between REGIN and VSS Nominal capacitor values specified. Recommend a 10% ceramic X5R type capacitor located close to the device. 0.1 µF
CREG25 External output capacitor for internal LDO between VCC 0.47 1 µF
tPUCD Power-up communication 250 ms

6.4 Thermal Information

THERMAL METRIC(1) bq34110 UNIT
TSSOP (PW)
14 PINS
RθJA Junction-to-ambient thermal resistance 103.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 31.9 °C/W
RθJB Junction-to-board thermal resistance 46.6 °C/W
ψJT Junction-to-top characterization parameter 2.0 °C/W
ψJB Junction-to-board characterization parameter 45.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics: Supply Current

TA= –40°C to 85°C, VREGIN = VBAT = 3.6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC_NORMAL Normal operating current Device in NORMAL mode, ILOAD > Sleep Current 133 µA
ISNOOZE(1) Sleep+ operation mode current Device in SNOOZE mode, ILOAD < Sleep Current 53 µA
ISLEEP(1) Low-power SLEEP mode current Device in SLEEP mode, ILOAD < Sleep Current 22 µA
ISHUTDOWN SHUTDOWN mode current Fuel gauge in SHUTDOWN mode, CE pin < VIL(CE) max 0.01 µA
(1) Specified by design. Not production tested.

6.6 Electrical Characteristics: Digital Input and Output DC Characteristics

TA= –40°C to 85°C, VREGIN = VBAT = 3.6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOL Output voltage, low (SCL, SDA, VEN, LEN, ALERT1, ALERT2 pins) IOL = 3 mA 0.4 V
VOH(PP) Output voltage, high IOH = –1 mA VREG25 – 0.5 V
VOH(OD) Output voltage, high (SDA, SCL, ALERT1, ALERT2 pins) External pull-up resistor connected to VREG25 VREG25 – 0.5 V
VIH(ALERT1) Input voltage, high (ALERT1 pin) 1.2 VREG25 + 0.3 V
VIL Input voltage, low –0.3 0.6 V
VIL(CE) Input voltage, low (CE pin) VREGIN = 2.7 to 4.5 V 0.8 V
VIH(CE) Input voltage, high (CE pin) VREGIN = 2.7 to 4.5 V 2.65 V
VIH(OD) Input voltage, high (SDA, SCL, ALERT2 pins) 1.2 5.5 V
ILKG Input leakage current (I/O pins) 0.3 µA

6.7 Electrical Characteristics: Power-On Reset

TA = –40°C to 85°C; typical values at TA = 25°C and VREGIN = 3.6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIT+ Positive-going battery voltage input at REGIN 2.20 V
VHYS Power-on reset hysteresis 115 mV

6.8 Electrical Characteristics: LDO Regulator

TA = 25°C, CREG25 = 1.0 μF, VREGIN = 3.6 V (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREG25 Regulator output voltage 2.7 V ≤ VREGIN ≤ 4.5 V, IOUT ≤ 16 mA
TA = –40°C to 85°C		 2.3 2.5 2.7 V
2.45 V ≤ VREGIN < 2.7 V, IOUT ≤ 3 mA
TA = –40°C to 85°C		 2.3
ISHORT(2) Short circuit current limit VREG25 = 0 V
TA = –40°C to 85°C		 250 mA
(1) LDO output current, IOUT, is the total load current. Use the LDO regulator to power the internal fuel gauge only.
(2) Specified by design. Not production tested.

6.9 Electrical Characteristics: Internal Temperature Sensor

TA = –40°C to 85°C, 2.4 V < VREG25 < 2.6 V; typical values at TA = 25°C and VREG25 = 2.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GTEMP Internal temperature sensor voltage gain –2 mV/°C

6.10 Electrical Characteristics: Low-Frequency Clock Oscillator

TA = –40°C to 85°C, 2.4 V < VREG25 < 2.6 V; typical values at TA = 25°C and VREG25 = 2.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f(LOSC) Operating frequency 32.768 kHz
f(EIO) Frequency error(1)(2) TA = 0°C to 60°C –1.5% 0.25% 1.5%
TA = –20°C to 70°C –2.5% 0.25% 2.5%
TA = –40°C to 85°C –4% 0.25% 4%
t(SXO) Start-up time(3) 500 µs
(1) The frequency drift is included and measured from the trimmed frequency at VREG25 = 2.5 V, TA = 25°C.
(2) The frequency error is measured from 32.768 kHz.
(3) The start-up time is defined as the time it takes for the oscillator output frequency to be ±3%.

6.11 Electrical Characteristics: High-Frequency Clock Oscillator

TA = –40°C to 85°C, 2.4 V < VREG25 < 2.6 V; typical values at TA = 25°C and VREG25 = 2.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f(LOSC) Operating frequency 8.389 MHz
f(EIO) Frequency error(1)(2) TA = 0°C to 60°C –2% 0.38% 2%
TA = –20°C to 70°C –3% 0.38% 3%
TA = –40°C to 85°C –4.5% 0.38% 4.5%
t(SXO) Start-up time(3) 5 ms
(1) The frequency drift is included and measured from the trimmed frequency at VREG25 = 2.5 V, TA = 25°C.
(2) The frequency error is measured from 8.389 MHz.
(3) The start-up time is defined as the time it takes for the oscillator output frequency to be ±3%.

6.12 Electrical Characteristics: Integrating ADC (Coulomb Counter)

TA = –40°C to 85°C, 2.4 V < VREG25 < 2.6 V; typical values at TA = 25°C and VREG25 = 2.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(SR) Differential input voltage range V(SR) = V(SRP) – V(SRN) –0.125 0.125 V
V(SRP), V(SRN) Input voltage range, V(SRP) and V(SRN) –0.125 0.125 V
tSR_CONV Conversion time Single conversion 1 s
Resolution 14 15 bits
VOS(SR) Input offset 10 µV
INL Integral nonlinearity error ±0.007% FSR(1)
ZIN(SR) Effective input resistance(2) 2.5 MΩ
ILKG(SR) Input leakage current(2) 0.3 µA
(1) Full-scale reference
(2) Specified by design. Not tested in production.

6.13 Electrical Characteristics: ADC (Temperature and Voltage Measurements)

TA = –40°C to 85°C, 2.4 V < VREG25 < 2.6 V; typical values at TA = 25°C and VREG25 = 2.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN((ADC) ADC input voltage range for BAT measurement Internal voltage divider inactive, internal VREF 0.05 1 V
Internal voltage divider activated, internal VREF 0.05 4.5 V
ADC input voltage for TS pin measurement 0 VREG25 V
tADC_CONV(1) Conversion time Single conversion 125 ms
Resolution 14 15 bits
VOS(ADC) Input offset 1 mV
ZADC_TS Effective input resistance (TS with internal pull-down activated)(1) 5 kΩ
ZADC_BAT Effective input resistance (BAT)(1) When not measuring cell voltage (internal voltage divider inactive) 8 MΩ
During measurement of cell voltage using internal divider (internal voltage divider active) 100 kΩ
ILKG(ADC) Input leakage current(1) 0.3 µA
(1) Specified by design. Not tested in production.

6.14 Electrical Characteristics: Data Flash Memory

TA = –40°C to 85°C, 2.4 V < VREG25 < 2.6 V; typical values at TA = 25°C and VREG25 = 2.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tDR Data retention(1) 10 Years
Flash –programming write cycles(1) 20,000 Cycles
tWORDPROG Word programming time(1) 2 ms
ICCPROG Flash-write supply current(1) 5 10 mA
(1) Specified by design. Not tested in production.

6.15 Timing Requirements: I2C-Compatible Interface Timing Characteristics

TA = –40°C to 85°C, 2.4 V < VREGIN = VBAT < 5 V; typical values at TA = 25°C and VREGIN = VBAT = 3.6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
tR SCL/SDA rise time 300 ns
tF SCL/SDA fall time 300 ns
tW(H) SCL pulse width (high) 600 ns
tW(L) SCL pulse width (low) 1.3 µs
tSU(STA) Setup for repeated start 600 ns
td(STA) Start to first falling edge of SCL 600 ns
tSU(DAT) Data setup time 100 ns
th(DAT) Data hold time 0 ns
tSU(STOP) Setup time for stop 600 ns
tBUF Bus free time between stop and start 66 µs
fSCL Clock frequency 400 kHz
bq34110 i2c_timing_diagram.gif Figure 1. I2C-Compatible Interface Timing Diagram

6.16 Typical Characteristics

bq34110 D001_SLUSBZ5.gif Figure 2. V(Err) Across VIN (0 mA)
bq34110 D003_SLUSBZ5.gif Figure 4. I(Err)
bq34110 D002_SLUSBZ5.gif Figure 3. V(Err) Across VIN (0 mA) for a 9-Series Configuration
bq34110 D004_SLUSBZ5.gif Figure 5. T(Err)