JAJSDK0 August   2017

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Supply Current
    6. 6.6  Digital Input and Output DC Characteristics
    7. 6.7  LDO Regulator, Wake-up, and Auto-Shutdown DC Characteristics
    8. 6.8  LDO Regulator, Wake-up, and Auto-Shutdown AC Characteristics
    9. 6.9  ADC (Temperature and Cell Measurement) Characteristics
    10. 6.10 Integrating ADC (Coulomb Counter) Characteristics
    11. 6.11 I2C-Compatible Interface Communication Timing
    12. 6.12 SHUTDOWN and WAKE-UP Timing
    13. 6.13 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Configuration
      2. 7.3.2  ALERT Interrupt and SHUTDOWN Wake-up
      3. 7.3.3  Voltage Measurement and Calibration
      4. 7.3.4  Temperature Measurement
      5. 7.3.5  Charging and Termination
      6. 7.3.6  Accumulated Charge Measurement
      7. 7.3.7  Gas Gauging
      8. 7.3.8  Battery Condition Warnings
      9. 7.3.9  Configuration Update
      10. 7.3.10 End-Of-Service Determination
      11. 7.3.11 Battery Level Threshold
      12. 7.3.12 Communications
        1. 7.3.12.1 I2C Interface
        2. 7.3.12.2 I2C Time Out
        3. 7.3.12.3 I2C Command Waiting Time
        4. 7.3.12.4 I2C Clock Stretching
      13. 7.3.13 Additional Data Memory Parameter Descriptions
    4. 7.4 Device Functional Modes
      1. 7.4.1 INITIALIZATION Mode
      2. 7.4.2 NORMAL Mode
      3. 7.4.3 SLEEP Mode
      4. 7.4.4 SHUTDOWN Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Getting Started
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 REGIN Voltage Sense Input
        2. 8.2.2.2 Integrated LDO Capacitor
        3. 8.2.2.3 Sense Resistor Selection
      3. 8.2.3 External Thermistor Support
      4. 8.2.4 Learning Load Enable (LEN) from Host
      5. 8.2.5 I2C
      6. 8.2.6 Temperature Sense
      7. 8.2.7 Application Curves
  9. 9 Power Supply Recommendation
    1. 9.1 Power Supply Decoupling
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 ツール
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VREGIN REGIN pin input voltage range –0.3 6 V
VSR SRP and SRN pins input voltage range –0.3 VREGIN + 0.3 V
Differential voltage across SRP and SRN. ABS(SRP – SRN) –0.3 2 V
VREG18 REG18 LDO output for capacitor only (not a supply pin) –0.3 2 V
VIOD Open-drain IO pins (SDA, SCL) –0.3 6 V
VALERT Open Drain Output / Control Input (ALERT) –0.3 6 V
VAI TS –0.3 REG18 + 0.3 V
TA Operating free-air temperature range –40 85 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

TA = 30°C and VREGIN = 3.6 V (unless otherwise noted)
MIN NOM MAX UNIT
CREGIN(1) External input capacitor for internal LDO between REGIN and VSS Nominal capacitor values specified. Recommend a 5% ceramic X5R-type capacitor located close to the device. 1 μF
CREG18(1) External output capacitor for internal LDO between REG18 and VSS 2.2 μF
VPU(1) External pullup voltage for open-drain pins (SDA, SCL, ALERT) 1.62 5.5 V
(1) Specified by design. Not production tested.

6.4 Thermal Information

THERMAL METRIC(1) bq34210-Q1 UNIT
PW (TSSOP)
14 PINS
RθJA Junction-to-ambient thermal resistance 111.0 °C/W
RθJCtop Junction-to-case (top) thermal resistance 37.9 °C/W
RθJB Junction-to-board thermal resistance 54.8 °C/W
ψJT Junction-to-top characterization parameter 3.0 °C/W
ψJB Junction-to-board characterization parameter 54.2 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance n/a °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Supply Current

TA = 30°C and VREGIN = 3.6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IREGIN(1) NORMAL mode current ILOAD > Sleep Current(2) 50 μA
ISLP(1) SLEEP mode current ILOAD < Sleep Current(2) 9 μA
ISD(1) SHUTDOWN mode current Fuel gauge in host commanded SHUTDOWN mode.
(LDO regulator output disabled) 		0.6 μA
(1) Specified by design. Not production tested.
(2) Wake Comparator disabled.

6.6 Digital Input and Output DC Characteristics

TA = –40°C to 85°C, typical values at TA = 30°C and VREGIN = 3.6 V (unless otherwise noted)(Force Note1)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH(OD) Input voltage, high(2) External pullup resistor to VPU VPU × 0.7 V
VIL Input voltage, low(2) 0.6 V
VOL Output voltage, low(2) 0.6 V
IOH Output source current, high(2) 0.5 mA
IOL(OD) Output sink current, low(2) –3 mA
CIN(1) Input capacitance(2)(3) 5 pF
Ilkg Input Leakage Current(2)(3) 1 μA
(1) Specified by design. Not production tested.
(2) SCL, SDA, ALERT
(3) TS

6.7 LDO Regulator, Wake-up, and Auto-Shutdown DC Characteristics

TA = –40°C to 85°C, typical values at TA = 30°C and VREGIN = 3.6 V (unless otherwise noted)(Force Note1)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREGIN Battery and regulator input 2.45 4.5 V
VREG18 Regulator output voltage 1.85 V
UVLOIT+ VREGIN undervoltage lock-out
LDO wake-up rising threshold		 2 V
UVLOIT– VREGIN undervoltage lock-out
LDO auto-shutdown falling threshold		 1.95 V
VWU+(1) ALERT (input) LDO Wake-up rising edge threshold(2) LDO Wake-up from SHUTDOWN mode 1.2 V
tALERT Minimum ALERT high time after VWU+ to initiate Wake up 1 ms
(1) Specified by design. Not production tested.
(2) If the device is commanded to SHUTDOWN via I2C with VREGIN > UVLOIT+, a wake-up rising edge trigger is required on ALERT.

6.8 LDO Regulator, Wake-up, and Auto-Shutdown AC Characteristics

TA = –40°C to 85°C, typical values at TA = 30°C and VREGIN = 3.6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tSHDN(1) SHUTDOWN entry time Time delay from SHUTDOWN command to LDO output disable. 250 ms
tSHUP(1) SHUTDOWN ALERT low time Minimum low time of ALERT (input) in SHUTDOWN before WAKEUP 10 μs
tREG18(1) Initial REG18 output delay 13 ms
tWUREG18(1) Wake-up REG18 output delay Time delay from rising edge of ALERT (input) to nominal REG18 output. 8 ms
tPUCD Power-up communication delay(2) Time delay from rising edge of REGIN to NORMAL mode (includes firmware initialization time). 250 ms
(1) Specified by design. Not production tested.
(2) tPUCD indicates when communication can begin. Measurements are not valid for up to 1 second after any reset.

6.9 ADC (Temperature and Cell Measurement) Characteristics

TA = –40°C to 85°C; typical values at TA = 30°C and VREGIN = 3.6 V (unless otherwise noted) (Force Note1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN(REGIN) REGIN pin voltage measurement range 2.45 4.5 V
tADC_CONV Conversion time 125 ms
Effective resolution 15 bits

6.10 Integrating ADC (Coulomb Counter) Characteristics

TA = –40°C to 85°C; typical values at TA = 30°C and VREGIN = 3.6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VSRCM Input voltage range of SRN, SRP pins VSS VREGIN + 100 mV V
VSRDM Input differential voltage range of VSRP–VSRN ±80 mV
tSR_CONV Conversion time Single conversion 1 s
Effective Resolution Single conversion 16 bits

6.11 I2C-Compatible Interface Communication Timing

TA = –40°C to 85°C; typical values at TA = 30°C and VREGIN = 3.6 V (unless otherwise noted) (Force Note1)(1)
MIN NOM MAX UNIT
Standard Mode (100 kHz)
td(STA) Start to first falling edge of SCL 4 μs
tw(L) SCL pulse duration (low) 4.7 μs
tw(H) SCL pulse duration (high) 4 μs
tsu(STA) Setup for repeated start 4.7 μs
tsu(DAT) Data setup time Host drives SDA 250 ns
th(DAT) Data hold time Host drives SDA 0 ns
tsu(STOP) Setup time for stop 4 μs
t(BUF) Bus free time between stop and start Includes Command Waiting Time 66 μs
tf SCL or SDA fall time(1)(2) 300 ns
tr SCL or SDA rise time(1)(2) 300 ns
fSCL Clock frequency(3) 100 kHz
Fast Mode (400 kHz)
td(STA) Start to first falling edge of SCL 600 ns
tw(L) SCL pulse duration (low) 1300 ns
tw(H) SCL pulse duration (high) 600 ns
tsu(STA) Setup for repeated start 600 ns
tsu(DAT) Data setup time Host drives SDA 100 ns
th(DAT) Data hold time Host drives SDA 0 ns
tsu(STOP) Setup time for stop 600 ns
t(BUF) Bus free time between stop and start Includes Command Waiting Time 66 μs
tf SCL or SDA fall time(1)(2) 300 ns
tr SCL or SDA rise time(1)(2) 300 ns
fSCL Clock frequency(3) 400 kHz
(1) Specified by design. Not production tested.
(2) Bus capacitance and pull-up resistance impact rise and fall times. View the rise and fall times to assist with debugging.
(3) If the clock frequency (fSCL) is > 100 kHz, use 1-byte write commands for proper operation. All other transactions types are supported at 400 kHz. (See I2C Interface and I2C Command Waiting Time.)
bq34210-Q1 tim_dia_i2c.gif Figure 1. I2C-Compatible Interface Timing Diagrams

6.12 SHUTDOWN and WAKE-UP Timing

bq34210-Q1 wake_shutdown.gif Figure 2. SHUTDOWN and WAKE-UP Timing Diagram

6.13 Typical Characteristics

bq34210-Q1 D001_SLUSCG1.gif
Figure 3. Impact of Applied (REGIN) Voltage on Voltage Measurement
bq34210-Q1 D002_SLUSCG1.gif
Figure 4. Internal Temperature Measurement Error