JAJSLN6C May 2012 – May 2021 BQ34Z100
PRODUCTION DATA
The HDQ interface is an asynchronous return-to-one protocol where a processor sends the command code to the device. With HDQ, the least significant bit (LSB) of a data byte (command) or word (data) is transmitted first. Note that the DATA signal on pin 12 is open-drain and requires an external pull-up resistor. The 8-bit command code consists of two fields: the 7-bit HDQ command code (bits 0–6) and the 1-bit R/W field (MSB Bit 7). The R/W field directs the device either to:
The HDQ peripheral can transmit and receive data as either an HDQ master or slave.
The return-to-one data bit frame of HDQ consists of three distinct sections. The first section is used to start the transmission by either the host or by the device taking the DATA pin to a logic-low state for a time tSTRH,B. The next section is for data transmission where the data is valid for a time tDSU after the negative edge used to start communication. The data is held until a time tDV, allowing the host or device time to sample the data bit. The final section is used to stop the transmission by returning the DATA pin to a logic-high state by at least a time tSSU after the negative edge used to start communication. The final logic-high state is held until the end of tCYCH,B, allowing time to ensure the transmission was stopped correctly. The timing for data and break communication is shown in Section 6.13.
HDQ serial communication is normally initiated by the host processor sending a break command to the device. A break is detected when the DATA pin is driven to a logic-low state for a time tB or greater. The DATA pin should then be returned to its normal ready high logic state for a time tBR. The device is now ready to receive information from the host processor.
The device is shipped in the I2C mode. TI provides tools to enable the HDQ peripheral.