JAJSLN6C May 2012 – May 2021 BQ34Z100
PRODUCTION DATA
Some BQ34Z100 pins are configured via the Pack Configuration data flash register, as indicated in Table 7-14. This register is programmed/read via the methods described in Section 7.2.3.1. The register is located at subclass = 64, offset = 0.
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
CHGDoDEoC | RSVD | VconsEN | RSVD | JEITA | LFPRelax | DoDWT | FConvEN |
CHGDoDEoC: | Enable DoD at EoC during charging only. True when set. Default is 1. Default setting is recommended. | |||
VconsEN: | Enable voltage consistency check. True when set. Default is 1. Default setting is recommended. | |||
LFPRelax: | Enables Lithium Iron Phosphate Relax | |||
DoDWT: | Enable Dod weighting for LiFePO4 support when chemical ID 400 series is selected. True when set. Default is 1 | |||
FConvEN: | Enable fast convergence algorithm. Default is 1. Default setting is recommended. | |||
RMFCC: | TBD |