JAJSCB3E June   2016  – April 2019 BQ35100

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Current Static Modes
    6. 6.6  Digital Input and Outputs
    7. 6.7  Power-On Reset
    8. 6.8  LDO Regulator
    9. 6.9  Internal Temperature Sensor
    10. 6.10 Internal Clock Oscillators
    11. 6.11 Integrating ADC (Coulomb Counter)
    12. 6.12 ADC (Temperature and Voltage Measurements)
    13. 6.13 Data Flash Memory
    14. 6.14 I2C-Compatible Interface Timing Characteristics
    15. 6.15 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Basic Measurement Systems
        1. 7.3.1.1 Voltage
        2. 7.3.1.2 Temperature
        3. 7.3.1.3 Coulombs
        4. 7.3.1.4 Current
      2. 7.3.2 Battery Gauging
        1. 7.3.2.1 ACCUMULATOR (ACC) Mode
        2. 7.3.2.2 STATE-OF-HEALTH (SOH) Mode
          1. 7.3.2.2.1 Low State-of-Health Alert
        3. 7.3.2.3 END-OF-SERVICE (EOS) Mode
          1. 7.3.2.3.1 Initial EOS Learning
            1. 7.3.2.3.1.1 End-Of-Service Detection
      3. 7.3.3 Power Control
      4. 7.3.4 Battery Condition Warnings
        1. 7.3.4.1 Battery Low Warning
        2. 7.3.4.2 Temperature Low Warning
        3. 7.3.4.3 Temperature High Warning
        4. 7.3.4.4 Battery Low SOH Warning
        5. 7.3.4.5 Battery EOS OCV BAD Warning
      5. 7.3.5 ALERT Signal
      6. 7.3.6 Lifetime Data Collection
      7. 7.3.7 SHA-1 Authentication
      8. 7.3.8 Data Commands
        1. 7.3.8.1 Command Summary
        2. 7.3.8.2 0x00, 0x01 AltManufacturerAccess() and 0x3E, 0x3F AltManufacturerAccess()
        3. 7.3.8.3 Control(): 0x00/0x01
      9. 7.3.9 Communications
        1. 7.3.9.1 I2C Interface
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Preparation for Gauging
        2. 8.2.2.2 Gauging Mode Selection
          1. 8.2.2.2.1 ACCUMULATOR Mode
            1. 8.2.2.2.1.1 STATE-OF-HEALTH (Voltage Correlation) Mode
            2. 8.2.2.2.1.2 END-OF-SERVICE (Resistance Correlation) Mode
        3. 8.2.2.3 Voltage Measurement Selection
        4. 8.2.2.4 Temperature Measurement Selection
        5. 8.2.2.5 Current Sense Resistor Selection
        6. 8.2.2.6 Expected Device Usage Profiles
        7. 8.2.2.7 Using the BQ35100 Fuel Gauge with a Battery and Capacitor in Parallel
          1. 8.2.2.7.1 ACCUMULATOR Mode
          2. 8.2.2.7.2 STATE-OF-HEALTH Mode
          3. 8.2.2.7.3 END-OF-SERVICE Mode
      3. 8.2.3 EOS Mode Load Pulse Synchronization
      4. 8.2.4 Benefits of the BQ35100 Gauge Compared to Alternative Monitoring Techniques
      5. 8.2.5 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Introduction
      2. 10.1.2 Power Supply Decoupling Capacitor
      3. 10.1.3 Capacitors
      4. 10.1.4 Communication Line Protection Components
    2. 10.2 Layout Example
      1. 10.2.1 Ground System
      2. 10.2.2 Kelvin Connections
      3. 10.2.3 Board Offset Considerations
    3. 10.3 ESD Spark Gap
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.2.3 Board Offset Considerations

Although the most important component for board offset reduction is the decoupling capacitor for VREG25, an additional benefit is possible by using this recommended pattern for the coulomb counter differential low-pass filter network. Maintain the symmetrical placement pattern shown for optimum current offset performance. Use symmetrical shielded differential traces, if possible, from the sense resistor to the 100-Ω resistors, as shown in Figure 17.

BQ35100 DiffConnect.gifFigure 17. Differential Connection Between SRP and SRN Pins with Sense Resistor