Table 2. Design Parameters

9.2.2.1 Inductor Selection

The bq40z60 has a 1000-kHz switching frequency to allow the use of small inductor and capacitor values. Inductor saturation current should be higher than the charging current (I_CHG) plus half the ripple current (I_RIPPLE):

Equation 1.

The inductor ripple current depends on input voltage (V_IN), duty cycle (D = V_OUT/V_IN), switching frequency (f_s) and inductance (L):

Equation 2.

The maximum inductor ripple current happens with D = 0.5 or close to 0.5. For example, the battery charging voltage range is from 9 V to 12.6 V for a 3-cell battery pack. For 20-V adaptor voltage, 10-V battery voltage gives the maximum inductor ripple current. Another example is a 4-cell battery: The battery voltage range is from 12 V to 16.8 V, and 12-V battery voltage gives the maximum inductor ripple current.

Usually inductor ripple is designed in the range of (20%–40%) maximum charging current as a trade-off between inductor size and efficiency for a practical design.

The bq40z60 has cycle-by-cycle charge undercurrent protection (UCP) by monitoring the charging-current sensing resistor to prevent negative inductor current. The typical UCP threshold is 5-mV falling edge corresponding to 0.5-A falling edge for a 10-mΩ charging-current sensing resistor.

9.2.2.2 Input Capacitor

The input capacitor should have enough ripple-current rating to absorb input switching ripple current. The worst-case RMS ripple current is half of the charging current when the duty cycle is 0.5. If the converter does not operate at 50% duty cycle, then the worst-case capacitor RMS current I_CIN occurs where the duty cycle is closest to 50% and can be estimated using the following equation:

Equation 3.

A low-ESR ceramic capacitor such as X7R or X5R is preferred for the input-decoupling capacitor and should be placed to the drain of the high-side MOSFET and source of the low-side MOSFET as close as possible. The voltage rating of the capacitor must be higher than the normal input voltage level. A 25-V or higher-rating capacitor is preferred for 20-V input voltage. 10-µF to 20-µF capacitance is suggested for typical of 3-A to 4-A charging current.

9.2.2.3 Output Capacitor

Output capacitor also should have enough ripple-current rating to absorb the output switching ripple current. The output capacitor RMS current I_COUT is given:

Equation 4.

The output capacitor voltage ripple can be calculated as follows:

Equation 5.

At a certain input/output voltage and switching frequency, the voltage ripple can be reduced by increasing the output filter LC. The bq40z60 has an internal loop compensator. To get good loop stability, the resonant frequency of the output inductor and output capacitor should be designed between 21 kHz and 27 kHz. The preferred ceramic capacitor has a 25-V or higher rating, X7R or X5R for a 4-cell application.

9.2.2.4 Power MOSFETs Selection

Two external N-CH MOSFETs are used for a synchronous switching battery charger. The gate drivers are internally integrated into the IC with 6 V of gate drive voltage. 30-V or higher voltage rating MOSFETs are preferred for 20-V input voltage, and 40 V or higher-rating MOSFETs are preferred for 20-V to 28-V input voltage.

Figure-of-merit (FOM) is usually used for selecting the proper MOSFET based on a tradeoff between the conduction loss and switching loss. For a top-side MOSFET, FOM is defined as the product of the MOSFET on-resistance, r_DS(on), and the gate-to-drain charge, Q_GD. For a bottom-side MOSFET, FOM is defined as the product of the MOSFET on-resistance, r_DS(on), and the total gate charge, Q_G.

Equation 6.

The lower the FOM value, the lower the total power loss. Usually a lower r_DS(on) has a higher cost with the same package size.

The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle (D = V_OUT/V_IN), charging current (I_CHG), the MOSFET on-resistance t_DS(on)), input voltage (V_IN), switching frequency (f_S), turn-on time (t_on), and turn-off time (t_off):

Equation 7.

The first item represents the conduction loss. Usually MOSFET r_DS(on) increases by 50% with 100°C junction temperature rise. The second term represents the switching loss. The MOSFET turn-on and turn-off times are given by:

Equation 8.

where Q_sw is the switching charge, I_on is the turn-on gate-driving current, and I_off is the turn-off gate driving current. If the switching charge is not given in the MOSFET data sheet, it can be estimated by gate-to-drain charge (Q_GD) and gate-to-source charge (Q_GS):

Equation 9.

Total gate-driving current can be estimated by the REGN voltage (V_REGN), MOSFET plateau voltage (V_plt), total turn-on gate resistance (R_on), and turn-off gate resistance (R_off) of the gate driver:

Equation 10.

The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in synchronous continuous-conduction mode:

Equation 11.

If the HSRP–HSRN voltage decreases below 5 mV (the charger is also forced into non-synchronous mode when the average HSRP–HSRN voltage is lower than 1.7 mV), the low-side FET is turned off for the remainder of the switching cycle to prevent negative inductor current. As a result, all the freewheeling current goes through the body diode of the bottom-side MOSFET. The maximum charging current in non-synchronous mode can be up to 1.6 A (0.5 A typ) for a 10-mΩ charging-current sensing resistor, considering IC tolerance. Choose the bottom-side MOSFET with either an internal Schottky or body diode capable of carrying the maximum non-synchronous mode charging current.

MOSFET gate-driver power loss contributes to the dominant losses on the controller IC when the buck converter is switching. The combined high side and low side MOSFET gate charge, Q_{g_total}, is proportional to the power dissipation of the IC, as shown in Equation 12:

Equation 12.

Choosing FETs with a lower Q_{g_total} will reduce power loss.

9.2.2.5 Input Filter Design

During adaptor hot plug-in, the parasitic inductance and input capacitor from the adaptor cable form a second-order system. The voltage spike at the VCC pin may be beyond the IC maximum voltage rating and damage the IC. The input filter must be carefully designed and tested to prevent an overvoltage event on the VCC pin.

There are several methods for damping or limiting the overvoltage spike during adaptor hot plug-in. An electrolytic capacitor with high ESR as an input capacitor can damp the overvoltage spike well below the IC maximum pin voltage rating. A high-current-capability TVS Zener diode can also limit the overvoltage level to an IC safe level. However, these two solutions may not have low cost or small size.

Figure 9 shows a cost-effective and small size solution. The R1 and C1 are composed of a damping RC network to damp the hot plug-in oscillation. As a result, the overvoltage spike is limited to a safe level. D1 is used for reverse voltage protection for the VCC pin (it can be the body diode of input ACFET). C2 is a VCC pin-decoupling capacitor and it should be placed as close as possible to the VCC pin. R2 and C2 form a damping RC network to further protect the IC from high dv/dt and high-voltage spike. The C2 value should be less than the C1 value so R1 can be dominant over the ESR of C1 to get enough of a damping effect for hot plug-in. The R1 and R2 packages must be sized to handle inrush-current power loss according to the resistor manufacturer’s datasheet. The filter component values always must be verified with the real application, and minor adjustments may be needed to fit in the real application circuit.

Figure 9. Input Filter