SLUSAW3D December   2014  – January 2017

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Voltage
    6. 7.6  Supply Current
    7. 7.7  Power Supply Control
    8. 7.8  Low-Voltage General Purpose I/O (TSx)
    9. 7.9  High-Voltage General Purpose I/O (GPIO0, GPIO1)
    10. 7.10 AFE Power-On Reset
    11. 7.11 Internal 1.8-V LDO
    12. 7.12 Current Wake Comparator
    13. 7.13 Coulomb Counter
    14. 7.14 CC Digital Filter
    15. 7.15 ADC
    16. 7.16 ADC Digital Filter
    17. 7.17 ADC Multiplexer
    18. 7.18 Cell Balancing Support
    19. 7.19 Cell Detach Detection
    20. 7.20 Internal Temperature Sensor
    21. 7.21 NTC Thermistor Measurement Support (ADCx)
    22. 7.22 High-Frequency Oscillator
    23. 7.23 Low-Frequency Oscillator
    24. 7.24 Voltage Reference 1
    25. 7.25 Voltage Reference 2
    26. 7.26 Instruction Flash
    27. 7.27 Data Flash
    28. 7.28 Current Protection Thresholds
    29. 7.29 N-CH FET Drive (CHG, DSG)
    30. 7.30 FUSE Drive (AFEFUSE)
    31. 7.31 Battery Charger Voltage Regulation (VFB)
    32. 7.32 Battery Charger Current Sense (HSRP, HSRN)
    33. 7.33 Battery Charger Precharge Current Sense (HSRP, HSRN)
    34. 7.34 AC Adapter Fault Detect (HSRN, VCC)
    35. 7.35 Battery Charger Overcurrent Detection (V)HSRP, (V)HSRN
    36. 7.36 Battery Charger Undercurrent Detection (V)HSRP, (V)HSRN
    37. 7.37 System Operation Detection (V)HSRN
    38. 7.38 Battery Overvoltage Comparator (VFB)
    39. 7.39 Regulator (REGN)
    40. 7.40 PWM High-Side Driver (HiDRV)
    41. 7.41 PWM Low-Side Driver (LoDRV)
    42. 7.42 PWM Information
    43. 7.43 Charger Power-Up Sequence
    44. 7.44 Thermal Shutdown Comparator
    45. 7.45 SMBus High Voltage I/O
    46. 7.46 SMBus
    47. 7.47 SMBus XL
    48. 7.48 Timing Requirements
    49. 7.49 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Safety Features
      2. 8.3.2  Analog Front End (AFE) Details
        1. 8.3.2.1 Wake Up Comparator
        2. 8.3.2.2 Cell Balancing Support
        3. 8.3.2.3 FET Drive
        4. 8.3.2.4 Fuse Drive
      3. 8.3.3  Charge Controller Details
        1. 8.3.3.1 Precharge Modes
        2. 8.3.3.2 Zero-Volt Charge Support
        3. 8.3.3.3 Charge Termination
      4. 8.3.4  Fuel Gauge and Control Details
        1. 8.3.4.1 Battery Trip Point (BTP)
        2. 8.3.4.2 Lifetime Data Logging Features
      5. 8.3.5  Authentication
      6. 8.3.6  LED Display
      7. 8.3.7  Internal Temperature Sensor
      8. 8.3.8  External Temperature Sensor Support
      9. 8.3.9  High Frequency Oscillator
      10. 8.3.10 Communications
        1. 8.3.10.1 SMBus On and Off State
        2. 8.3.10.2 SBS Commands
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input Capacitor
        3. 9.2.2.3 Output Capacitor
        4. 9.2.2.4 Power MOSFETs Selection
        5. 9.2.2.5 Input Filter Design
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

QFN Package (RHB)
32 Pins

Pin Functions

PIN DESCRIPTION
NAME NUMBER I/O(1)
BAT 1 P Battery input pin. Primary power supply
PBI 2 P Power supply backup input pin
VC4 3 IA Sense voltage input pin for the most positive cell, balance current input for the most positive cell, and battery stack measurement input
VC3 4 IA Sense voltage input pin for the third most positive cell, balance current input for the third most positive cell, and return balance current for the most positive cell
VC2 5 IA Sense voltage input pin for the second most positive cell, balance current input for the second most positive cell, and return balance current for the most positive cell
VC1 6 IA Sense voltage input pin for the least positive cell, balance current input for the least positive cell, and return balance current for the second most positive cell
SRN 7 IA Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN, where SRP is the top of the sense resistor.
SRP 8 IA Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN, where SRP is the top of the sense resistor.
VSS 9 P Device ground
TS1 10 IA Thermistor input for temperature sensor channel 1
TS2 11 IA Thermistor input for temperature sensor channel 2
TS3 12 IA Thermistor input for temperature sensor channel 3
TS4 13 IA Thermistor input for temperature sensor channel 4
GPIO0 14 I/O Multi-function I/O (open drain). For more information, see IO Configuration in the bq40z60 Technical Reference Manual (SLUUA04).
GPIO1 15 I/O Multi-function I/O (open drain). See IO Configuration in the bq40z60 Technical Reference Manual (SLUUA04).
SMBD 16 I/OD SMBus data pin
SMBC 17 I/OD SMBus clock pin
VFB 18 IA Feedback sense input for charger control loop
HSRN 19 IA High sense resistor negative node input
HSRP 20 IA High sense resistor positive node input
AFEFUSE 21 O Fuse drive output pin
VCC 22 P Power supply input
REGN 23 O Charger FET gate drive regulator
PGND 24 P Power ground
LODRV 25 O Low side charging FET gate control output
PH 26 I/O Charger phase signal input
HIDRV 27 O High side charging FET gate control output
BTST 28 IA High side bootstrap capacitor input
ACFET 29 O AC FET gate control output
DSG 30 O N-CH FET drive output pin
ACP 31 IA Adapter input pin
CHG 32 O N-CH FET drive output pin
(1) P = Power Connection, O = Digital Output, IA = Analog Input, I = Digital Input, I/OD = Digital Input/Output