SLUSAW3D December 2014 – January 2017
PRODUCTION DATA.
VALUE | UNIT | ||
---|---|---|---|
V(ESD) Rating | HBM(1) | ±2000 | V |
CDM(2) | ±500 | V |
THERMAL METRIC(1) | bq40z60 | UNIT | |
---|---|---|---|
RHB (VQFN) | |||
32 PINS | |||
RθJA, High K | Junction-to-ambient thermal resistance | 36 | °C/W |
RθJC(top) | Junction-to-case(top) thermal resistance | 31.5 | °C/W |
RθJB | Junction-to-board thermal resistance | 8 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.5 | °C/W |
ψJB | Junction-to-board characterization parameter | 7.9 | °C/W |
RθJCbot | Junction-to-case(bottom) thermal resistance | 2.2 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VCC | Device Operating Range | Operation with charger enabled | 4.0 | 25 | V | ||
Operation with charger disabled | 2.5 | 25 | |||||
VCC-UV | Undervoltage lock out | VCC falling | 2.2 | 2.45 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
INORMAL | NORMAL mode(1) | CPU = ACTIVE, HFO = ON, ADC_FILTER = ON, CC_FILTER = ON, LFO = ON, REG18 = ON, CHG = ON, DSG = ON, ADC = ON, CC = ON, Charger Enabled, No Communication | 1250 | 1850 | µA | ||
CPU = HALT, HFO = ON, ADC_FILTER = ON, CC_FILTER = ON, LFO = ON, REG18 = ON, CHG = ON, DSG = ON, ADC = ON, CC = ON, Charger Disabled, No Communication | 310 | 445 | |||||
ISLEEP | SLEEP mode(1) | CPU = HALT, HFO = ON, ADC_FILTER = OFF, CC_FILTER = OFF, LFO = ON, REG18 = ON, CHG = ON, DSG = ON, ADC = OFF, CC = OFF, Charger Disabled, No Communication | 122 | 183 | µA | ||
CPU = HALT, HFO = OFF, ADC_FILTER = OFF, CC_FILTER = OFF, LFO = ON, REG18 = ON, CHG = ON, DSG = ON, ADC = OFF, CC = OFF, Charger Disabled, No Communication | 92 | 138 | |||||
CPU = HALT, HFO = ON, ADC_FILTER = OFF, CC_FILTER = OFF, LFO = ON, REG18 = ON, CHG = OFF, DSG = OFF, ADC = OFF, CC = OFF, Charger Disabled, No Communication | 82 | 128 | |||||
CPU = HALT, HFO = OFF, ADC_FILTER = OFF, CC_FILTER = OFF, LFO = ON, REG18 = ON, CHG = OFF, DSG = OFF, ADC = OFF, CC = OFF, Charger Disabled, No Communication | 52 | 83 | |||||
ISHUTDOWN | SHUTDOWN mode | CPU = HALT, HFO = OFF, ADC_FILTER = OFF, CC_FILTER = OFF, LFO = OFF, REG18 = OFF, CHG = OFF, DSG = OFF, ADC = OFF, CC = OFF, Charger Disabled, No Communication | 0.5 | 2 | µA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VSWITCHOVER– | BAT to VCC switchover voltage | VBAT < VSWITCHOVER– | 2.0 | 2.1 | 2.2 | V |
VSWITCHOVER+ | VCC to BAT switchover voltage | VBAT > VSWITCHOVER– + VHYS | 3.0 | 3.1 | 3.2 | V |
VHYS | Switchover voltage hysteresis | VSWITCHOVER+ – VSWITCHOVER– | 1000 | mV | ||
ILKG | Input leakage current | BAT pin, BAT = 0 V, VCC = 25 V | 1 | µA | ||
VCC pin, BAT = 25 V, VCC = 0 V | 1 | |||||
BAT and VCC pins, BAT = 0 V, VCC = 0 V, PBI = 25 V | 1 | |||||
RPD | Internal pulldown resistance | ACP | 30 | 40 | 50 | kΩ |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VIH | High-level input | 0.65 × VREG | V | |||
VIL | Low-level input | 0.35 × VREG | V | |||
VOH | Output voltage high | IOH = –1.0 mA | 0.75 × VREG | V | ||
IOH = –10 µA | ||||||
VOL | Output voltage low | IOL = 1.0 mA | 0.2 × VREG | V | ||
CIN | Input capacitance | 5 | pF | |||
ILKG | Input leakage current | 1 | µA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VREGIT– | Negative-going voltage input | VREG | 1.51 | 1.55 | 1.59 | V |
VHYS | Power-on reset hysteresis | VREGIT+ – VREGIT– | 70 | 100 | 130 | mV |
tRST | Power-on reset time | 200 | 300 | 400 | µs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VREG | Regulator voltage | 1.6 | 1.8 | 2.0 | V | ||
ΔVO(TEMP) | Regulator output over temperature | ΔVREG/ΔTA, IREG = 10 mA | ±0.25% | ||||
ΔVO(LINE) | Line regulation | ΔVREG/ΔVBAT, VBAT = 10 mA | –0 .6% | 0.5% | |||
ΔVO(LOAD) | Load regulation | ΔVREG/ΔIREG, IREG = 0 mA to 10 mA | –1.5% | 1.5% | |||
IREG | Regulator output current limit | VREG = 0.9 × VREG(NOM), VIN > 2.2 V | 20 | mA | |||
ISC | Regulator short-circuit current limit | VREG = 0 × VREG(NOM) | 25 | 40 | 50 | mA | |
PSRRREG | Power supply rejection ratio | ΔVBAT/ΔVREG, IREG = 10 mA ,VIN > 2.5 V, f = 10 Hz | 40 | dB | |||
VSLEW | Slew rate enhancement voltage threshold | 1.58 | 1.65 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VWAKE | Wake voltage threshold | VWAKE = VSRP – VSRN | ±0.3 | ±0.625 | ±0.9 | mV |
VWAKE = VSRP – VSRN | ±0.6 | ±1.25 | ±1.8 | |||
VWAKE = VSRP – VSRN | ±1.2 | ±2.5 | ±3.6 | |||
VWAKE = VSRP – VSRN | ±2.4 | ±5.0 | ±7.2 | |||
VWAKE(DRIFT) | Temperature drift of VWAKE accuracy | 0.5% | °C | |||
tWAKE | Time from application of current to wake | 0.25 | 0.5 | ms | ||
tWAKE(SU) | Wake comparator startup time | 500 | 1000 | µs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Input voltage range | –0.1 | 0.1 | V | ||
Full scale range | –VREF1/10 | VREF1/10 | V | ||
Integral nonlinearity(2) | 16-bit, Best fit over input voltage range | ±5.2 | ±22.3 | LSB | |
Offset error | 16-bit, Post-calibration | ±5 | ±10 | µV | |
Offset error drift | 15-bit + sign, Post-calibration | 0.2 | 0.3 | µV/°C | |
Gain error | 15-bit + sign, Over input voltage range | ±0.2% | ±0.8% | FSR(3) | |
Gain error drift | 15-bit + sign, Over input voltage range | 150 | PPM/°C | ||
Effective input resistance | 2.5 | MΩ |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Conversion time | Single conversion | 250 | ms | ||
Effective resolution | Single conversion | 15 | Bits |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Input voltage range | Internal reference (VREF1) | –0.2 | 1 | V | |
External reference (VREG) | –0.2 | 0.8 × VREG | |||
Full scale range | VFS = VREF1 or VREG | –VFS | VFS | V | |
Integral nonlinearity(2) | 16-bit, Best fit, –0.1 V to 0.8 × VREF1 | ±6.6 | LSB | ||
16-bit, Best fit, –0.2 V to –0.1 V | ±13.1 | ||||
Offset error(3) | 16-bit, Post-calibration, VFS = VREF1 | ±67 | ±157 | µV | |
Offset error drift | 16-bit, Post-calibration, VFS = VREF1 | 0.6 | 3 | µV/°C | |
Gain error | 16-bit, –0.1 V to 0.8 × VFS | ±0.2% | ±0.8% | FSR | |
Gain error drift | 16-bit, –0.1 V to 0.8 × VFS | 150 | PPM/°C | ||
Effective input resistance | 8 | MΩ |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Conversion time | ADCTL[SPEED1, SPEED0] = 0, 0 | 31.25 | ms | ||
ADCTL[SPEED1, SPEED0] = 0, 1 | 15.63 | ||||
ADCTL[SPEED1, SPEED0] = 1, 0 | 7.81 | ||||
ADCTL[SPEED1, SPEED0] = 1, 1 | 1.95 | ||||
Resolution | No missing codes, ADCTL[SPEED1, SPEED0] = 0, 0 | 16 | Bits | ||
Effective resolution | With sign, ADCTL[SPEED1, SPEED0] = 0, 0 | 14 | 15 | Bits | |
With sign, ADCTL[SPEED1, SPEED0] = 0, 1 | 13 | 14 | |||
With sign, ADCTL[SPEED1, SPEED0] = 1, 0 | 11 | 12 | |||
With sign, ADCTL[SPEED1, SPEED0] = 1, 1 | 9 | 10 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
K | Scaling factor | VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3 | 0.1980 | 0.2000 | 0.2020 | — |
VC4–VSS, ACP–VSS | 0.049 | 0.050 | 0.051 | |||
VREF2 | 0.490 | 0.500 | 0.510 | |||
HSRN–VSS | 0.049 | 0.050 | 0.051 | |||
VIN | Input voltage range | VC4–VSS, ACP–VSS | –0.2 | 20 | V | |
TSx | –0.2 | 0.8 × VREF1 | ||||
TSx | –0.2 | 0.8 × VREG | ||||
ILKG | Input leakage current | VC1, VC2, VC3, VC4, cell balancing off, cell detach detection off, ADC multiplexer off | 1 | µA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
RCB | Internal cell balance resistance | RDS(ON) for internal FET switch at 2 V < VDS < 4 V | 200 | Ω |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ICD | Internal cell detach check current | VCx > VSS + 0.8 V | 30 | 50 | 70 | µA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VTEMP | Internal temperature sensor voltage drift | VTEMPP | –1.9 | –2.0 | –2.1 | mV/°C |
VTEMPP – VTEMPN, assured by design | 0.177 | 0.178 | 0.179 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
RNTC(PU) | Internal pullup resistance | 14.4 | 18 | 21.6 | kΩ | |
RNTC(DRIFT) | Resistance drift over temperature | –360 | –280 | –200 | PPM/°C |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fHFO | Operating frequency | 16.78 | MHz | |||
fHFO(ERR) | Frequency error | TA = –20°C to 70°C, includes frequency drift | –2.5% | ±0.25% | 2.5% | |
TA = –40°C to 85°C, includes frequency drift | –3.5% | ±0.25% | 3.5% | |||
tHFO(SU) | Start-up time | TA = –20°C to 85°C, CLKCTL[HFRAMP] = 1, oscillator frequency within +/–3% of nominal | 4 | ms | ||
CLKCTL[HFRAMP] = 0, oscillator frequency within +/–3% of nominal | 100 | µs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fLFO | Operating frequency | 262.144 | kHz | |||
fLFO(ERR) | Frequency error | TA = –20°C to 70°C, includes frequency drift | –1.5% | ±0.25% | 1.5% | |
TA = –40°C to 85°C, includes frequency drift | –2.5 | ±0.25 | 2.5 | |||
fLFO(FAIL) | Failure detection frequency | 30 | 80 | 100 | kHz |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VREF1 | Internal reference voltage | TA = 25°C, after trim | 1.21 | 1.215 | 1.22 | V |
VREF1(DRIFT) | Internal reference voltage drift | TA = 0°C to 60°C, after trim | ±50 | PPM/°C | ||
TA = –40°C to 85°C, after trim | ±80 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VREF2 | Internal reference voltage | TA = 25°C, after trim | 1.22 | 1.225 | 1.23 | V |
VREF2(DRIFT) | Internal reference voltage drift | TA = 0°C to 60°C, after trim | ±50 | PPM/°C | ||
TA = –40°C to 85°C, after trim | ±80 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Data retention | 10 | Years | ||||
Flash programming write cycles | 1000 | Cycles | ||||
tPROGWORD | Word programming time | TA = –40°C to 85°C | 40 | µs | ||
tMASSERASE | Mass-erase time | TA = –40°C to 85°C | 40 | ms | ||
tPAGEERASE | Page-erase time | TA = –40°C to 85°C | 40 | ms | ||
IFLASHREAD | Flash-read current | TA = –40°C to 85°C | 2 | mA | ||
IFLASHWRITE | Flash-write current | TA = –40°C to 85°C | 5 | mA | ||
IFLASHERASE | Flash-erase current | TA = –40°C to 85°C | 15 | mA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Data retention | 10 | Years | ||||
Flash programming write cycles | 20000 | Cycles | ||||
tPROGWORD | Word programming time | TA = –40°C to 85°C | 40 | µs | ||
tMASSERASE | Mass-erase time | TA = –40°C to 85°C | 40 | ms | ||
tPAGEERASE | Page-erase time | TA = –40°C to 85°C | 40 | ms | ||
IFLASHREAD | Flash-read current | TA = –40°C to 85°C | 1 | mA | ||
IFLASHWRITE | Flash-write current | TA = –40°C to 85°C | 5 | mA | ||
IFLASHERASE | Flash-erase current | TA = –40°C to 85°C | 15 | mA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOCD | OCD detection threshold voltage range | VOCD = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1 | –16.6 | –100 | mV | ||
VOCD = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0 | –8.3 | –50 | |||||
ΔVOCD | OCD detection threshold voltage program step | VOCD = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1 | –5.56 | mV | |||
VOCD = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0 | –2.78 | ||||||
VSCC | SCC detection threshold voltage range | VSCC = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1 | 44.4 | 200 | mV | ||
VSCC = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0 | 22.2 | 100 | |||||
ΔVSCC | SCC detection threshold voltage program step | VSCC = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1 | 22.2 | mV | |||
VSCC = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0 | 11.1 | ||||||
VSCD1 | SCD1 detection threshold voltage range | VSCD1 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1 | –44.4 | –200 | mV | ||
VSCD1 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0 | –22.2 | –100 | |||||
ΔVSCD1 | SCD1 detection threshold voltage program step | VSCD1 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1 | –22.2 | mV | |||
VSCD1 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0 | –11.1 | ||||||
VSCD2 | SCD2 detection threshold voltage range | VSCD2 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1 | –44.4 | –200 | mV | ||
VSCD2 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0 | –22.2 | –100 | |||||
ΔVSCD2 | SCD2 detection threshold voltage program step | VSCD2 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1 | –22.2 | mV | |||
VSCD2 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0 | –11.1 | ||||||
VOFFSET | OCD, SCC, and SCDx offset error | Post-trim | –2.5 | 2.5 | mV | ||
VSCALE | OCD, SCC, and SCDx scale error | No trim | –10% | 10% | |||
Post-trim | –5% | 5% |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
Output voltage ratio | RatioDSG = (VDSG – VBAT)/VBAT, 2.2 V < VBAT < 4.07 V, 10 MΩ between HSRN and DSG | 2.133 | 2.333 | 2.533 | — | ||
RatioCHG = (VCHG – VBAT)/VBAT, 2.2 V < VBAT < 4.07 V, 10 MΩ between BAT and CHG | 2.133 | 2.333 | 2.533 | ||||
RatioACFET = (VACFET – VBAT)/VBAT, 2.2 V < VBAT < 4.07 V, 10 MΩ between ACP and ACFET | 2.133 | 2.333 | 2.533 | ||||
V(FETON) | Output voltage, CHG and DSG on | VDSG(ON) = VDSG – VBAT, VBAT ≥ 4.07 V, 10 MΩ between VHSRN and DSG, VBAT = 18 V | 9.0 | 9.5 | 10 | V | |
VCHG(ON) = VCHG – VBAT, VBAT ≥ 4.07 V, 10 MΩ between BAT and CHG, VBAT = 18 V | 9.0 | 9.5 | 10 | ||||
ACFET | VACFET(ON) = VACFET – VBAT, VBAT ≥ 4.07 V, 10 MΩ between ACP and ACFET, VBAT = 18 V | 9.0 | 9.5 | 10 | |||
V(FETOFF) | Output voltage, CHG and DSG off | VDSG(OFF) = VDSG – VACP, 10 MΩ between HSRN and DSG | –0.4 | 0.4 | V | ||
VCHG(OFF) = VCHG – VBAT, 10 MΩ between BAT and CHG | –0.4 | 0.4 | |||||
ACFET | VACFET(OFF) = VACFET – VACP, VBAT ≥ 4.07 V, 10 MΩ between ACP and ACFET, VBAT = 18 V | –0.4 | 0.4 | ||||
tR | Rise time | VDSG from 0% to 35% VDSG(ON)(TYP), VACP ≥ 2.2 V, CL = 4.7 nF between DSG and VHSRN, 5.1 kΩ between DSG and CL, 10 MΩ between VHSRN and DSG | 200 | 500 | µs | ||
VCHG from 0% to 35% VCHG(ON)(TYP), VACP ≥ 2.2 V, CL = 4.7 nF between CHG and BAT, 5.1 kΩ between CHG and CL, 10 MΩ between BAT and CHG | 200 | 500 | |||||
VACFET from 0% to 35% VACFET(ON)(TYP), VACP ≥ 2.2 V, CL = 4.7 nF between ACFET and ACP, 5.1 kΩ between CHG and CL, 10 MΩ between ACP and ACFET | 200 | 500 | |||||
tF | Fall time | VDSG from VDSG(ON)(TYP) to 1 V, VACP ≥ 2.2 V, CL = 4.7 nF between DSG and ACP, 5.1 kΩ between DSG and CL, 10 MΩ between ACP and DSG | 40 | 300 | µs | ||
VCHG from VCHG(ON)(TYP) to 1 V, VACP ≥ 2.2 V, CL = 4.7 nF between CHG and BAT, 5.1 kΩ between CHG and CL, 10 MΩ between BAT and CHG | 40 | 200 | |||||
VACFET from VACFET(ON)(TYP) to 1 V, VACP ≥ 2.2 V, CL = 4.7 nF between ACFET and ACP, 5.1 kΩ between CHG and CL, 10 MΩ between ACP and ACFET | 40 | 200 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | Output voltage high | VBAT ≥ 8 V, CL = 1 nF, IAFEFUSE = 0 µA | 6 | 7 | 8.65 | V | |
VBAT < 8 V, CL = 1 nF, IAFEFUSE = 0 µA | VBAT – 0.1 | VBAT | |||||
VIH | High-level input | 1.5 | 2.0 | 2.5 | V | ||
IAFEFUSE(PU) | Internal pullup current | VBAT ≥ 8 V, VAFEFUSE = VSS | 150 | 330 | nA | ||
RAFEFUSE | Output impedance | 2 | 2.6 | 3.2 | kΩ | ||
CIN | Input capacitance | 5 | pF | ||||
tDELAY | Fuse trip detection delay | 128 | 256 | µs | |||
tRISE | Fuse output rise time | VBAT ≥ 8 V, CL = 1 nF, VOH = 0 V to 5 V | 5 | 20 | µs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VFB | Regulation range | Based on internal DAC reference setting | 0.61 | 1.22 | V | ||
VFBACC | Voltage feedback accuracy | VFB = 1.22 V | –2% | 2% | |||
VFB(STEPS) | Programmable regulation steps | 2.5 | mV | ||||
RVFB | Total feedback resistor divider range | 500 | 700 | kΩ |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VIN(Normal range) | Differential Input range | DAC range for current measurement | 2 | 100 | mV | ||
VACC | Measurement accuracy | VHSRP – VHSRN = 50 mV, RSense= 10 mΩ | –5% | 5% |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VIN(Normal range) | Differential Input range | DAC range for current measurement | 2 | 20 | mV | ||
VACC | Measurement accuracy | VHSRP – VHSRN = 2 mV, RSense= 10 mΩ (VHSRN > 2.3 V) |
–70% | 70% |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VHSRN – VCC | AC adapter input fault detect | Battery > AC adapter input (Falling) | 150 | 225 | 300 | mV | |
VHys | Recovery hysteresis | AC adapter input > Battery (Rising) | 50 | 100 | 150 | mV |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
IOC(max) | Charger overcurrent threshold | Charging current as a percentage of max sense voltage range | 180 | 200 | mV | ||
IOC(min) | Charger overcurrent threshold | Minimum charging overcurrent detected | 45 | 55 | mV |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
IUC(Detect) | Detect under current for negative inductor current | VHSRP – VHSRN < 0 mV, for negative inductor current, VHSRP > 2.3 V | 1 | 5 | 16 | mV | |
IUC(Non-synch) | Minimum sense voltage to enter non-synchronous mode | 1.7 | mV |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VHSRN | Input voltage for operation | VHSRN Falling | 2.05 | 2.15 | 2.25 | V | |
VHys | Recovery hysteresis | VHSRN Rising | 100 | 150 | 200 | mV |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOV(max) | Battery over-voltage detection | VFB > Set value (Rising) | 106% | ||||
VOV(Recovery) | Battery over-voltage recovery | VFB < VOV (Falling) | 103% |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VLODRV | Gate drive for low side charger FET | VCC > 10 V, ILoad = 0 to 60 mA | 5.7 | 6.0 | 6.3 | V | |
I SC | Short circuit current limit | VLODRV = 0 V | 60 | mA | |||
VREGN | Power good indicator | VREGN Rising | 3.6 | 3.68 | 3.75 | V | |
VHys | Hysteresis | VREGN Falling | 240 | 260 | 280 | mV |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
RON | Driver turn ON resistance | VBTST – VPH ≥ 5.5 V | 6.0 | 8.6 | Ω | ||
ROFF | Driver turn OFF resistance | VFB < VOV (Falling) | 2.5 | 3.3 | Ω | ||
VBOOTSTRAP | Bootstrap refresh comparator | VCC = 4 V to 6 V | 2.6 | 2.9 | V | ||
VCC > 6 V | 3.9 | 4.1 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
RON | Driver turn ON resistance | VREGN – VPGND ≥ 5.5 V | 5.2 | 7.6 | Ω | ||
ROFF | Driver turn OFF resistance | VFB < VOV (Falling) | 1.9 | 2.4 | Ω |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
tDEADTIME | Deadtime between FET driver output switching | 30 | ns | ||||
Duty cycle | 99.5% | ||||||
fSW | PWM switching frequency | 0.8 | 1.0 | 1.1 | MHz |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
tDELAY | Power-up sequence | 8 | ms | ||||
tSS(STEPS) | Soft start steps | 8 | |||||
tSS(STEP TIME) | Soft start time | 2 | ms |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
TSHUTDOWN | 135 | 145 | C | ||||
THys | 12 | C |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VIH | Input voltage high | SMBC, SMBD, VREG = 1.8 V | 1.3 | V | |||
VIL | Input voltage low | SMBC, SMBD, VREG = 1.8 V | 0.8 | V | |||
VOL | Output low voltage | SMBC, SMBD, VREG = 1.8 V, IOL = 1.5 mA | 0.4 | V | |||
CIN | Input capacitance | 5 | pF | ||||
ILKG | Input leakage current | 1 | µA | ||||
RPD | pulldown resistance | 0.7 | 1.0 | 1.3 | MΩ |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fSMB | SMBus operating frequency | SLAVE mode, SMBC 50% duty cycle | 10 | 100 | kHz | |
fMAS | SMBus master clock frequency | MASTER mode, no clock low slave extend | 51.2 | kHz | ||
tBUF | Bus free time between start and stop | 4.7 | µs | |||
tHD(START) | Hold time after (repeated) start | 4.0 | µs | |||
tSU(START) | Repeated start setup time | 4.7 | µs | |||
tSU(STOP) | Stop setup time | 4.0 | µs | |||
tHD(DATA) | Data hold time | 300 | ns | |||
tSU(DATA) | Data setup time | 250 | ns | |||
tTIMEOUT | Error signal detect time | 25 | 35 | ms | ||
tLOW | Clock low period | 4.7 | µs | |||
tHIGH | Clock high period | 4.0 | 50 | µs | ||
tR | Clock rise time | 10% to 90% | 1000 | ns | ||
tF | Clock fall time | 90% to 10% | 300 | ns | ||
tLOW(SEXT) | Cumulative clock low slave extend time | 25 | ms | |||
tLOW(MEXT) | Cumulative clock low master extend time | 10 | ms |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fSMBXL | SMBus XL operating frequency | SLAVE mode | 40 | 400 | kHz | |
tBUF | Bus free time between start and stop | 4.7 | µs | |||
tHD(START) | Hold time after (repeated) start | 4.0 | µs | |||
tSU(START) | Repeated start setup time | 4.7 | µs | |||
tSU(STOP) | Stop setup time | 4.0 | µs | |||
tTIMEOUT | Error signal detect time | 5 | 20 | ms | ||
tLOW | Clock low period | 20 | µs | |||
tHIGH | Clock high period | 20 | µs |
MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|
CURRENT PROTECTION TIMING | ||||||
tOCD | OCD detection delay time | 1 | 31 | ms | ||
ΔtOCD | OCD detection delay time program step | 2 | ms | |||
tSCC | SCC detection delay time | 0 | 915 | µs | ||
ΔtSCC | SCC detection delay time program step | 61 | µs | |||
tSCD1 | SCD1 detection delay time | PROTECTION_CONTROL[SCDDx2] = 0 | 0 | 915 | µs | |
PROTECTION_CONTROL[SCDDx2] = 1 | 0 | 1850 | ||||
ΔtSCD1 | SCD1 detection delay time program step | PROTECTION_CONTROL[SCDDx2] = 0 | 61 | µs | ||
PROTECTION_CONTROL[SCDDx2] = 1 | 121 | |||||
tSCD2 | SCD2 detection delay time | PROTECTION_CONTROL[SCDDx2] = 0 | 0 | 458 | µs | |
PROTECTION_CONTROL[SCDDx2] = 1 | 0 | 915 | ||||
ΔtSCD2 | SCD2 detection delay time program step | PROTECTION_CONTROL[SCDDx2] = 0 | 30.5 | µs | ||
PROTECTION_CONTROL[SCDDx2] = 1 | 61 | |||||
tDETECT | Current fault detect time | VSRP – VSRN = VT – 3 mV for OCD, SCD1, and SC2, VSRP – VSRN = VT + 3 mV for SCC | 160 | µs | ||
tACC | Current fault delay time accuracy | Max delay setting | –10% | 10% |