SLPS585 March   2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Powering bq500101 And Gate Drivers
      2. 7.3.2 Undervoltage Lockout Protection (UVLO)
      3. 7.3.3 Integrated Boost-Switch
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application Curves
    3. 8.3 System Example
      1. 8.3.1 Power Loss Curves
      2. 8.3.2 Safe Operating Area (SOA) Curves
      3. 8.3.3 Normalized Curves
        1. 8.3.3.1 Calculating Power Loss and SOA
          1. 8.3.3.1.1 Design Example
          2. 8.3.3.1.2 Calculating Power Loss
          3. 8.3.3.1.3 Calculating SOA Adjustments
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Recommended PCB Design Overview
      2. 9.1.2 Electrical Performance
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Trademarks
    2. 10.2 Electrostatic Discharge Caution
    3. 10.3 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Drawing
    2. 11.2 Recommended PCB Land Pattern
    3. 11.3 Recommended Stencil Opening

パッケージ・オプション

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発注情報

7 Detailed Description

7.1 Overview

The bq500101 NexFET™ Power Stage is a highly optimized design for use in wireless power transmitter designs. The bq500101 can also be used for synchronous buck applications.

7.2 Functional Block Diagram

bq500101 New_Block_Diag2.gif

7.3 Feature Description

7.3.1 Powering bq500101 And Gate Drivers

An external VDD voltage is required to supply the integrated gate driver device and provide the necessary gate drive power for the MOSFETS. A 1-µF 10-V X5R or higher ceramic capacitor is recommended to bypass VDD pin to PGND. A bootstrap circuit to provide gate drive power for the Control FET is also included. The bootstrap supply to drive the Control FET is generated by connecting a 100-nF 16-V X5R ceramic capacitor CBOOT between BOOT and BOOT_R pins. An optional RBOOT resistor in series with CBOOT can be used to slow down the turn on speed of the Control FET and reduce voltage spikes on the VSW node. A typical 1 Ω to 4.7 Ω value is a compromise between switching loss and VSW spike amplitude.

7.3.2 Undervoltage Lockout Protection (UVLO)

The undervoltage lockout (UVLO) comparator evaluates the VDD voltage level. As VVDD rises, both the Control FET and Sync FET gates hold actively low at all times until VVDD reaches the higher UVLO threshold (VUVLO_H)., Then the driver becomes operational and responds to PWM command. If VDD falls below the lower UVLO threshold (VUVLO_L = VUVLO_H – Hysteresis), the device disables the driver and drives the outputs of the Control FET and Sync FET gates actively low. Figure 1 shows this function.

bq500101 v12218_lusba6.gif Figure 1. UVLO Operation

7.3.3 Integrated Boost-Switch

To maintain a BOOT-VSW voltage close to VDD (to get lower conduction losses on the high-side FET), the conventional diode between the VDD pin and the BOOT pin is replaced by a FET which is gated by the DRVL signal.