SLUSB96A November   2012  – December 2015

 

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Fundamentals
      2. 7.1.2 Wireless Power Consortium (WPC)
      3. 7.1.3 Power Transfer
      4. 7.1.4 Communication
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Capacitor Selection
      2. 7.3.2  A6 Coil Specification
      3. 7.3.3  Option Select Pins
      4. 7.3.4  LED Modes
      5. 7.3.5  Parasitic Metal Object Detect (PMOD) and Foreign Object Detection (FOD)
      6. 7.3.6  Shut Down by Thermal Sensor or Trigger
      7. 7.3.7  Fault Handling and Indication
      8. 7.3.8  Power Transfer Start Signal
      9. 7.3.9  Power-On Reset
      10. 7.3.10 External Reset, RESET Pin
      11. 7.3.11 Trickle Charge and CS100
      12. 7.3.12 Current Monitoring Requirements
      13. 7.3.13 Overcurrent Protection
      14. 7.3.14 MSP430G2101 Low Power Supervisor
      15. 7.3.15 All Unused Pins
  8. 8 Application and Implementation
    1. 8.1 Typical Application
      1. 8.1.1 Detailed Design Procedure
        1. 8.1.1.1 Input Regulator
        2. 8.1.1.2 Power Trains
        3. 8.1.1.3 Signal Processing Components
        4. 8.1.1.4 Low-Power Supervisor
        5. 8.1.1.5 Disabling Low-Power Supervisor Mode
        6. 8.1.1.6 Input Power Requirements
    2. 8.2 System Examples
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Community Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9 Layout

9.1 Layout Guidelines

Careful PCB layout practice is critical to proper system operation. There are many references on proper PCB layout techniques. A few good tips are repeated here:

The TX layout requires a 4-layer PCB layout for best ground plane technique. A 2-layer PCB layout can be achieved though not as easily. Ideally, the approach to the layer stack-up has been:

  • Layer 1 component placement and as much ground plane as possible.
  • Layer 2 clean ground.
  • Layer 3 finish routing.
  • Layer 4 clean ground.

Thus, the circuitry is virtually sandwiched between grounds. This minimizes EMI noise emissions and also provides a noise-free voltage reference plane for device operation.

Keep as much copper as possible. Make sure the bq500410A GND pins and the power pad have a continuous flood connection to the ground plane. The power pad should also be stitched to the ground plane, which also acts as a heat sink for the bq500410A. A good GND reference is necessary for proper bq500410A operation, such as analog-digital conversion, clock stability and best overall EMI performance.

Separate the analog ground plane from the power ground plane and use only ONE tie point to connect grounds. Having several tie points defeats the purpose of separating the grounds.

The COMM return signal from the resonant tank should be routed as a differential pair. This is intended to reduce stray noise induction. The frequencies of concern warrant low-noise analog signaling techniques, such as differential routing and shielding, but the COMM signal lines do not need to be impedance matched.

The DC-DC buck regulator used from the 12-V input supplies the bq500410A with 3.3 V. Typically a single-chip controller solution with integrated power FET and synchronous rectifier or outboard diode is used. Pull in the buck inductor and power loop as close as possible to create a tight loop. Likewise, the power-train, full-bridge components should be pulled together as tight as possible. See the bq500410A EVM for an example of a good layout technique.