JAJSF16D march 2013 – september 2020 BQ51013B
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VUVLO | Undervoltage lockout | VRECT: 0 V → 3 V | 2.5 | 2.7 | 2.8 | V | |
VHYS-UVLO | Hysteresis on UVLO | VRECT: 3 V → 2 V | 250 | mV | |||
VRECT-OVP | Input overvoltage threshold | VRECT: 5 V → 16 V | 14.5 | 15 | 15.5 | V | |
VHYS-OVP | Hysteresis on OVP | VRECT: 16 V → 5 V | 150 | mV | |||
VRECT-Th1 | Dynamic VRECT Threshold 1 | ILOAD < 0.1 x IIMAX (ILOAD rising) | 7.08 | V | |||
VRECT-Th2 | Dynamic VRECT Threshold 2 | 0.1 x IIMAX < ILOAD < 0.2 x IIMAX (ILOAD rising) | 6.28 | V | |||
VRECT-Th3 | Dynamic VRECT Threshold 3 | 0.2 x IIMAX < ILOAD < 0.4 x IIMAX (ILOAD rising) | 5.53 | V | |||
VRECT-Th4 | Dynamic VRECT Threshold 4 | ILOAD > 0.4 x IIMAX (ILOAD rising) | 5.11 | V | |||
VRECT-Track | VRECT TRACKING | In current limit, voltage above VOUT | VOUT+0.25 | V | |||
ILOAD | ILOAD Hysteresis for dynamic VRECT thresholds as a % of IILIM | ILOAD falling | 4% | ||||
VRECT-DPM | Rectifier undervoltage protection, restricts IOUT at VRECT-DPM | 3 | 3.1 | 3.2 | V | ||
VRECT-REV | Rectifier reverse voltage protection at the output | VRECT-REV = VOUT - VRECT, VOUT = 10 V | 8 | 9 | V | ||
QUIESCENT CURRENT | |||||||
IRECT | Active chip quiescent current consumption from RECT | ILOAD = 0 mA, 0°C ≤ TJ ≤ 85°C | 8 | 10 | mA | ||
ILOAD = 300 mA, 0°C ≤ TJ ≤ 85°C | 2 | 3 | mA | ||||
IOUT | Quiescent current at the output when wireless power is disabled (Standby) | VOUT = 5 V, 0°C ≤ TJ ≤ 85°C | 20 | 35 | µA | ||
ILIM SHORT CIRCUIT | |||||||
RILIM-SHORT | Highest value of ILIM resistance to ground (RILIM) considered a fault (short). Monitored for IOUT > 100 mA | RILIM: 200 Ω → 50 Ω. IOUT latches off, cycle power to reset | 120 | Ω | |||
tDGL-Short | Deglitch time transition from ILIM short to IOUT disable | 1 | ms | ||||
IILIM_SHORT,OK | ILIM-SHORT,OK enables the ILIM short comparator when IOUT is greater than this value | ILOAD: 0 mA → 200 mA | 116 | 145 | 165 | mA | |
IILIM_SHORT,OK HYST | Hysteresis for ILIM-SHORT,OK comparator | ILOAD: 0 mA → 200 mA | 30 | mA | |||
IOUT | Maximum output current limit, CL | Maximum ILOAD that will be delivered for 1 ms when ILIM is shorted | 2.45 | A | |||
OUTPUT | |||||||
VOUT-REG | Regulated output voltage | ILOAD = 1000 mA | 4.95 | 5.00 | 5.04 | V | |
ILOAD = 10 mA | 4.96 | 5.01 | 5.06 | ||||
KILIM | Current programming factor for hardware protection | RILIM = KILIM / IILIM, where IILIM is the hardware current limit. IOUT = 1 A | 303 | 314 | 321 | AΩ | |
KIMAX | Current programming factor for the nominal operating current | IIMAX = KIMAX / RILIM where IMAX is the maximum normal operating current. IOUT = 1 A | 262 | AΩ | |||
IOUT | Current limit programming range | 1500 | mA | ||||
ICOMM | Current limit during WPC communication | IOUT > 300 mA | IOUT + 50 | mA | |||
IOUT < 300 mA | 330 | 381 | 426 | mA | |||
tHOLD | Hold off time for the communication current limit during start-up | 1 | s | ||||
TS / CTRL FUNCTIONALITY | |||||||
VTS-Bias | Internal TS Bias Voltage (VTS is the voltage at the TS/CTRL pin, VTS-Bias is thet internal bias voltage) | ITS-Bias < 100 µA (periodically driven see tTS/CTRL) | 2 | 2.2 | 2.4 | V | |
VCOLD | Rising threshold | VTS-Bias: 50% → 60% | 56.5 | 58.7 | 60.8 | %VTS-Bias | |
VCOLD-Hyst | Falling hysteresis | VTS-Bias: 60% → 50% | 2 | %VTS-Bias | |||
VHOT | Falling threshold | VTS-Bias: 20% → 15% | 18.5 | 19.6 | 20.7 | %VTS-Bias | |
VHOT-Hyst | Rising hysteresis | VTS-Bias: 15% → 20% | 3 | %VTS-Bias | |||
VCTRL-High | Voltage on CTRL pin for a high | 0.2 | 5 | V | |||
VCTRL-Low | Voltage on CTRL pin for a low | 0 | 0.05 | mV | |||
tTS/CTRL-Meas | Time period of TS/CTRL measurements (when VTS-Bias is being driven internally) | Synchronous to the communication period | 24 | ms | |||
tTS-Deglitch | Deglitch time for all TS comparators | 10 | ms | ||||
RTS | Pullup resistor for the NTC network. Pulled up to VTB-Bias | 18 | 20 | 22 | kΩ | ||
THERMAL PROTECTION | |||||||
TJ-SD | Thermal shutdown temperature | 155 | °C | ||||
TJ-Hys | Thermal shutdown hysteresis | 20 | °C | ||||
OUTPUT LOGIC LEVELS ON CHG | |||||||
VOL | Open-drain CHG pin | ISINK = 5 mA | 500 | mV | |||
IOFF | CHG leakage current when disabled | V CHG = 20 V | 1 | µA | |||
COMM PIN | |||||||
RDS(ON) | COMM1 and COMM2 | VRECT = 2.6 V | 1.5 | Ω | |||
fCOMM | Signaling frequency on COMM pin | 2 | kbps | ||||
IOFF | COMMx pin leakage current | VCOMM1 = 20 V, VCOMM2 = 20 V | 1 | µA | |||
CLAMP PIN | |||||||
RDS(ON) | CLAMP1 and CLAMP2 | 0.8 | Ω | ||||
ADAPTER ENABLE | |||||||
VAD-Pres | VAD Rising threshold voltage | VAD 0 V → 5 V | 3.5 | 3.6 | 3.8 | V | |
VAD-PresH | VAD hysteresis | VAD 5 V → 0 V | 400 | mV | |||
IAD | Input leakage current | VRECT = 0 V, VAD = 5 V | 60 | μA | |||
RAD | Pullup resistance from AD-EN to OUT when adapter mode is disabled and VOUT > VAD, EN-OUT | VAD = 0 V, VOUT = 5 V | 200 | 350 | Ω | ||
VAD-Diff | Voltage difference between VAD and V AD-EN when adapter mode is enabled | VAD = 5 V, 0°C ≤ TJ ≤ 85°C | 3 | 4.5 | 5 | V | |
SYNCHRONOUS RECTIFIER | |||||||
IOUT-SR | IOUT at which the synchronous rectifier enters half-synchronous mode, SYNC_EN | ILOAD 200 mA → 0 mA | 80 | 100 | 135 | mA | |
IOUT-SRH | Hysteresis for IOUT,SR (full-synchronous mode enabled) | ILOAD 0 mA → 200 mA | 30 | mA | |||
VHS-DIODE | High-side diode drop when the rectifier is in half-synchronous mode | IAC-VRECT = 250 mA and TJ = 25°C | 0.7 | V | |||
EN1 AND EN2 | |||||||
VIL | Input low threshold for EN1 and EN2 | 0.4 | V | ||||
VIH | Input high threshold for EN1 and EN2 | 1.3 | V | ||||
RPD | EN1 and EN2 pulldown resistance | 200 | kΩ | ||||
ADC (WPC RELATED MEASUREMENTS AND COEFFICIENTS) | |||||||
IOUT SENSE | Accuracy of the current sense over the load range | IOUT = 750 mA - 1000 mA | –1.5% | 0% | 0.9% |