JAJSSA8 November   2023 BQ76905

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Supply Current
    6. 6.6  Digital I/O
    7. 6.7  REGOUT LDO
    8. 6.8  Voltage References
    9. 6.9  Coulomb Counter
    10. 6.10 Coulomb Counter Digital Filter
    11. 6.11 Current Wake Detector
    12. 6.12 Analog-to-Digital Converter
    13. 6.13 Cell Balancing
    14. 6.14 Internal Temperature Sensor
    15. 6.15 Thermistor Measurement
    16. 6.16 Hardware Overtemperature Detector
    17. 6.17 Internal Oscillator
    18. 6.18 Charge and Discharge FET Drivers
    19. 6.19 Comparator-Based Protection Subsystem
    20. 6.20 Timing Requirements—I2C Interface, 100-kHz Mode
    21. 6.21 Timing Requirements—I2C Interface, 400-kHz Mode
    22. 6.22 Timing Diagram
    23. 6.23 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Configuration
      1. 7.3.1 Commands and Subcommands
      2. 7.3.2 Configuration Using OTP or Registers
      3. 7.3.3 Device Security
    4. 7.4 Device Hardware Features
      1. 7.4.1  Voltage ADC
      2. 7.4.2  Coulomb Counter and Digital Filters
      3. 7.4.3  Protection FET Drivers
      4. 7.4.4  Voltage References
      5. 7.4.5  Multiplexer
      6. 7.4.6  LDOs
      7. 7.4.7  Standalone Versus Host Interface
      8. 7.4.8  ALERT Pin Operation
      9. 7.4.9  Low Frequency Oscillator
      10. 7.4.10 I2C Serial Communications Interface
    5. 7.5 Measurement Subsystem
      1. 7.5.1 Voltage Measurement
        1. 7.5.1.1 Voltage ADC Scheduling
        2. 7.5.1.2 Unused VC Pins
        3. 7.5.1.3 General Purpose ADCIN Functionality
      2. 7.5.2 Current Measurement and Charge Integration
      3. 7.5.3 Internal Temperature Measurement
      4. 7.5.4 Thermistor Temperature Measurement
      5. 7.5.5 Factory Trim and Calibration
    6. 7.6 Protection Subsystem
      1. 7.6.1 Protections Overview
      2. 7.6.2 Primary Protections
      3. 7.6.3 CHG Detector
      4. 7.6.4 Cell Open-Wire Protection
      5. 7.6.5 Diagnostic Checks
    7. 7.7 Cell Balancing
    8. 7.8 Device Operational Modes
      1. 7.8.1 Overview of Operational Modes
      2. 7.8.2 NORMAL Mode
      3. 7.8.3 SLEEP Mode
      4. 7.8.4 DEEPSLEEP Mode
      5. 7.8.5 SHUTDOWN Mode
      6. 7.8.6 CONFIG_UPDATE Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plot
      4. 8.2.4 Random Cell Connection Support
      5. 8.2.5 Startup Timing
      6. 8.2.6 FET Driver Turn-Off
      7. 8.2.7 Usage of Unused Pins
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-06446294-AB63-4DC2-B9C1-D67A10E9E9FA-low.svg Figure 5-1 BQ76905 Pinout
Table 5-1 Pin Functions
PIN I/O TYPE DESCRIPTION
NO. NAME
1 VC3A I IA Sense voltage input pin for the negative terminal of the fourth cell from the bottom of the stack, and return balance current for the fourth cell from the bottom of the stack
2 VC3B I IA Sense voltage input pin for the third cell from the bottom of the stack, and balance current input for the third cell from the bottom of the stack.
1 VC2 I IA Sense voltage input pin for the second cell from the bottom of the stack, balance current input for the second cell from the bottom of the stack, and return balance current for the third cell from the bottom of the stack
2 VC1 I IA Sense voltage input pin for the first cell from the bottom of the stack, balance current input for the first cell from the bottom of the stack, and return balance current for the second cell from the bottom of the stack
3 VC0 I IA Sense voltage input pin for the negative terminal of the first cell from the bottom of the stack, and return balance current for the first cell from the bottom of the stack
6 SRP I IA Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN, where SRP is the top of the sense resistor. A charging current generates a positive voltage at SRP relative to SRN.
7 SRN I IA Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN, where SRN is the bottom of the sense resistor. A charging current generates a positive voltage at SRP relative to SRN.
8 TS I/O I/OA Thermistor or general-purpose ADC input and functions as wakeup from SHUTDOWN
9 DSG O OA NMOS Discharge FET drive output pin
10 CHG O OA NMOS Charge FET drive output pin
11 VSS — P Device ground
12 SCL I/O I/OD I2C serial communication bus clock
13 SDA I/O I/OD I2C serial communication bus data
14 ALERT O OD Digital interrupt output pin
15 REGOUT O OA LDO output, which can be programmed for 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V
16 REGSRC I IA Input pin for REGOUT LDO, also functions as supply for the CHG and DSG FET drivers
17 BAT I P Primary power supply input pin
18 VC5 I IA Sense voltage input pin for the fifth cell from the bottom of the stack, balance current input for the fifth cell from the bottom of the stack, and the top-of-stack measurement point
19 VC4A I IA Sense voltage input pin for negative terminal of the fifth cell from the bottom of the stack, and return balance current for the fifth cell from the bottom of the stack
20 VC4B I IA Sense voltage input pin for the fourth cell from the bottom of the stack, and balance current input for the fourth cell from the bottom of the stack