A simplified application schematic for
a 5-series battery pack is shown in BQ76905 5-Series Cell Typical Implementation (Simplified Schematic),
using the BQ76905 together with an external secondary protector, a host
microcontroller, and a communications transceiver. This configuration uses low-side
CHG and DSG FETs in series. Several points to consider in an implementation are
included below:
- Use
a
series diode
at
the BAT pin, together with a capacitor from the pin to VSS. These components
allow the device to continue operating for a short time when a pack short
circuit occurs, which may cause the top-of-stack voltage to drop to
approximately 0 V. In this case, the diode prevents the BAT pin from being
pulled low with the stack, and the device
continues
to operate, drawing current from the capacitor.
Generally,
operation is only required for a short time, until the device detects the short
circuit event and disables the DSG FET. A Schottky diode can be used if low
voltage pack operation is needed, or a conventional diode can be used
otherwise.
- The FET CHG and DSG drivers use
the REGSRC pin for their supply, so the user may also prefer to include a diode
between the top of stack and the REGSRC pin, similar to that used for the BAT
pin. If any resistance (> 1 Ω) is included in series between the top of stack
and the REGSRC pin, it is recommended to include a
1-μF
capacitor at the REGSRC pin to VSS. The REGSRC pin can be shorted to the BAT pin
and a single diode used, but this may result in the BAT pin voltage dropping
more rapidly during a short circuit event due to the increased loading of the
REGOUT regulator drawing from the REGSRC pin.
- The recommended minimum voltage
on the VC0 to VC3A pins extends down to –0.2 V, while the recommended minimum
voltage on the VC4A, VC4B, and VC5 pins is limited to 2.0 V, relative to VSS.
This restriction exists to ensure the specified cell voltage measurement
accuracy.
- TI recommends using
100-Ω
resistors in series with the SRP and SRN pins, and a 100 nF with optional 100 pF
differential filter capacitance between the pins for filtering. The routing of
these components, together with the sense resistor, to the pins should be
minimized and fully symmetric, with all components recommended to stay on the
same side of the PCB with the device. Capacitors connected from the pins to VSS
can provide filtering of common mode transients from reaching the pins, but they
may also have a slight impact on current measurement performance.
- The filter network connected
between the sense resistor and the SRP and SRN pins introduces an analog filter
delay that can be important when fast current protections are required, such as
in determining the short circuit in discharge (SCD) time until FETs are
disabled. If the delay introduced by this network is too long, the resistance
and capacitance values can be reduced.
Thishas
a tradeoff of providing less analog filtering of high frequency components.
- Due to thermistors often being
attached to cells and possibly needing long wires to connect back to the device,
it may be helpful to add a capacitor from the thermistor pin to the device VSS.
However, it is important to not use too large of a value of capacitor,
because
this
affects
the settling time when the thermistor is biased and measured periodically. A
rule of thumb is to keep the time constant of the circuit < 5% of the
measurement time. When Settings:Configuration:DA
Config[IADCSPEED1:0] = 0x0, the measurement time is approximately 3
ms. When using this speed setting, the time constant should generally be less
than (20 kΩ) × C, so a capacitor less than 7.5 nF is recommended. When using
faster speed settings, the capacitor value should be reduced accordingly.
A full schematic of a basic monitor
circuit based on the BQ76905 for a 5-series battery pack is shown below. Figure 8-9 shows the board layout.