JAJSS72 November   2023 BQ76907

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information bq76907
    5. 6.5  Supply Current
    6. 6.6  Digital I/O
    7. 6.7  REGOUT LDO
    8. 6.8  Voltage References
    9. 6.9  Coulomb Counter
    10. 6.10 Coulomb Counter Digital Filter
    11. 6.11 Current Wake Detector
    12. 6.12 Analog-to-Digital Converter
    13. 6.13 Cell Balancing
    14. 6.14 Internal Temperature Sensor
    15. 6.15 Thermistor Measurement
    16. 6.16 Hardware Overtemperature Detector
    17. 6.17 Internal Oscillator
    18. 6.18 Charge and Discharge FET Drivers
    19. 6.19 Comparator-Based Protection Subsystem
    20. 6.20 Timing Requirements - I2C Interface, 100kHz Mode
    21. 6.21 Timing Requirements - I2C Interface, 400kHz Mode
    22. 6.22 Timing Diagram
    23. 6.23 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Configuration
      1. 7.3.1 Commands and Subcommands
      2. 7.3.2 Configuration Using OTP or Registers
      3. 7.3.3 Device Security
    4. 7.4 Device Hardware Features
      1. 7.4.1  Voltage ADC
      2. 7.4.2  Coulomb Counter and Digital Filters
      3. 7.4.3  Protection FET Drivers
      4. 7.4.4  Voltage References
      5. 7.4.5  Multiplexer
      6. 7.4.6  LDOs
      7. 7.4.7  Standalone Versus Host Interface
      8. 7.4.8  ALERT Pin Operation
      9. 7.4.9  Low Frequency Oscillator
      10. 7.4.10 I2C Serial Communications Interface
    5. 7.5 Measurement Subsystem
      1. 7.5.1 Voltage Measurement
        1. 7.5.1.1 Voltage ADC Scheduling
        2. 7.5.1.2 Unused VC Pins
        3. 7.5.1.3 General Purpose ADCIN Functionality
      2. 7.5.2 Current Measurement and Charge Integration
      3. 7.5.3 Internal Temperature Measurement
      4. 7.5.4 Thermistor Temperature Measurement
      5. 7.5.5 Factory Trim and Calibration
    6. 7.6 Protection Subsystem
      1. 7.6.1 Protections Overview
      2. 7.6.2 Primary Protections
      3. 7.6.3 CHG Detector
      4. 7.6.4 Cell Open-Wire Protection
      5. 7.6.5 Diagnostic Checks
    7. 7.7 Cell Balancing
    8. 7.8 Device Operational Modes
      1. 7.8.1 Overview of Operational Modes
      2. 7.8.2 NORMAL Mode
      3. 7.8.3 SLEEP Mode
      4. 7.8.4 DEEPSLEEP Mode
      5. 7.8.5 SHUTDOWN Mode
      6. 7.8.6 CONFIG_UPDATE Mode
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plot
      4. 8.2.4 Random Cell Connection Support
      5. 8.2.5 Startup Timing
      6. 8.2.6 FET Driver Turn-Off
      7. 8.2.7 Usage of Unused Pins
  10. Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Introduction to Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

I2C Serial Communications Interface

The I2C serial communications interface in the BQ76907 acts as a target device and supports rates up to 400 kHz with an optional CRC check. The BQ76907 will initially power up by default in a mode determined by the OTP settings factory programmed by TI. The host can change the CRC mode setting while in CONFIG_UPDATE mode, then the new setting will take effect upon exit of CONFIG_UPDATE mode.

The I2C device address (as an 8-bit value including target address and R/W bit) is set by default as 0x10 (write), 0x11 (read), which can also be changed by the configuration setting.

The communications interface includes programmable timeout capability, with the internal I2C bus logic reset when an enabled timeout occurs. This is described in detail in the BQ76907 Technical Reference Manual.

An I2C write transaction is shown in Figure 7-1. Block writes are allowed by sending additional data bytes before the Stop. The I2C logic will auto-increment the register address after each data byte. The shaded regions show when the device may be clock stretching.


GUID-56F0F98C-65F0-46D3-A5C2-D11F56D89F1A-low.gif

Figure 7-1 I2C Write

The CRC check is enabled by setting a data memory bit. When enabled, the CRC is calculated as follows:

  • Note that the CRC is reset after each data byte and after each stop.
  • In a single-byte write transaction, the CRC is calculated over the target address, register address, and data.
  • In a block write transaction, the CRC for the first data byte is calculated over the target address, register address, and data. The CRC for subsequent data bytes is calculated over the data byte only.

The CRC polynomial is x8 + x2 + x + 1, and the initial value is 0.

When the target detects an invalid CRC, the I2C target will NACK the CRC, which causes the I2C target to go to an idle state.

Figure 7-2 shows a read transaction using a Repeated Start. The shaded regions show when the device may be clock stretching.


GUID-49AD6A3C-A0CD-4FC9-ACDC-A0B913031E88-low.gif

Figure 7-2 I2C Read with Repeated Start

Figure 7-3 shows a read transaction where a Repeated Start is not used, for example if not available in hardware. For a block read, the controller ACK’s each data byte except the last and continues to clock the interface. The I2C block will auto-increment the register address after each data byte. The shaded regions show when the device may be clock stretching.


GUID-A701E975-A2D6-45D0-B815-7F30C01296C1-low.gif

Figure 7-3 I2C Read Without Repeated Start

When enabled, the CRC for a read transaction is calculated as follows:

  • Note that the CRC is reset after each data byte and after each stop.
  • In a single-byte read transaction using a repeated start, the CRC is calculated beginning at the first start, so will include the target address, the register address, then the target address with read bit set, then the data byte.
  • In a single-byte read transaction using a stop after the initial register address, the CRC is reset after the stop, so will only include the target address with read bit set and the data byte.
  • In a block read transaction using repeated starts, the CRC for the first data byte is calculated beginning at the first start and will include the target address, the register address, then the target address with read bit set, then the data byte. The CRC for subsequent data bytes is calculated over the data byte only.
  • In a block read transaction using a stop after the initial register address, the CRC is reset after the stop, so will only include the target address with read bit set and the first data byte. The CRC for subsequent data bytes is calculated over the data byte only.

The CRC polynomial is x8 + x2 + x + 1, and the initial value is 0.

When the controller detects an invalid CRC, the I2C controller will NACK the CRC, which causes the I2C target to go to an idle state.

For more information, see the BQ76907 Technical Reference Manual.