JAJSS72 November   2023 BQ76907

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information bq76907
    5. 6.5  Supply Current
    6. 6.6  Digital I/O
    7. 6.7  REGOUT LDO
    8. 6.8  Voltage References
    9. 6.9  Coulomb Counter
    10. 6.10 Coulomb Counter Digital Filter
    11. 6.11 Current Wake Detector
    12. 6.12 Analog-to-Digital Converter
    13. 6.13 Cell Balancing
    14. 6.14 Internal Temperature Sensor
    15. 6.15 Thermistor Measurement
    16. 6.16 Hardware Overtemperature Detector
    17. 6.17 Internal Oscillator
    18. 6.18 Charge and Discharge FET Drivers
    19. 6.19 Comparator-Based Protection Subsystem
    20. 6.20 Timing Requirements - I2C Interface, 100kHz Mode
    21. 6.21 Timing Requirements - I2C Interface, 400kHz Mode
    22. 6.22 Timing Diagram
    23. 6.23 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Configuration
      1. 7.3.1 Commands and Subcommands
      2. 7.3.2 Configuration Using OTP or Registers
      3. 7.3.3 Device Security
    4. 7.4 Device Hardware Features
      1. 7.4.1  Voltage ADC
      2. 7.4.2  Coulomb Counter and Digital Filters
      3. 7.4.3  Protection FET Drivers
      4. 7.4.4  Voltage References
      5. 7.4.5  Multiplexer
      6. 7.4.6  LDOs
      7. 7.4.7  Standalone Versus Host Interface
      8. 7.4.8  ALERT Pin Operation
      9. 7.4.9  Low Frequency Oscillator
      10. 7.4.10 I2C Serial Communications Interface
    5. 7.5 Measurement Subsystem
      1. 7.5.1 Voltage Measurement
        1. 7.5.1.1 Voltage ADC Scheduling
        2. 7.5.1.2 Unused VC Pins
        3. 7.5.1.3 General Purpose ADCIN Functionality
      2. 7.5.2 Current Measurement and Charge Integration
      3. 7.5.3 Internal Temperature Measurement
      4. 7.5.4 Thermistor Temperature Measurement
      5. 7.5.5 Factory Trim and Calibration
    6. 7.6 Protection Subsystem
      1. 7.6.1 Protections Overview
      2. 7.6.2 Primary Protections
      3. 7.6.3 CHG Detector
      4. 7.6.4 Cell Open-Wire Protection
      5. 7.6.5 Diagnostic Checks
    7. 7.7 Cell Balancing
    8. 7.8 Device Operational Modes
      1. 7.8.1 Overview of Operational Modes
      2. 7.8.2 NORMAL Mode
      3. 7.8.3 SLEEP Mode
      4. 7.8.4 DEEPSLEEP Mode
      5. 7.8.5 SHUTDOWN Mode
      6. 7.8.6 CONFIG_UPDATE Mode
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plot
      4. 8.2.4 Random Cell Connection Support
      5. 8.2.5 Startup Timing
      6. 8.2.6 FET Driver Turn-Off
      7. 8.2.7 Usage of Unused Pins
  10. Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Introduction to Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Detailed Design Procedure

  • Determine the number of series cells
    • This value depends on the cell chemistry and the load requirements of the system. For example, to support a minimum battery voltage of 18 V using Li-CO2 type cells with a cell minimum voltage of 3 V, at least 6-series cells are required.
    • For the correct cell connections, see Usage of Unused Pins.
  • Protection FET selection and configuration
    • The BQ76907 device is designed for use with low-side NFET protection.
    • The configuration should be selected for series versus parallel FETs, which may lead to different FET selection for charge versus discharge direction.
    • These FETs should be rated for the maximum:
      • Voltage, which should be approximately 5 V (DC) to 10 V (peak) per series cell.
      • Current, which should be calculated based on both the maximum DC current and the maximum transient current with some margin.
      • Power dissipation, which can be a factor of the RDS(ON) rating of the FET, the FET package, and the PCB design.
  • Sense resistor selection
    • The resistance value should be selected to maximize the input range of the coulomb counter but not exceed the absolute maximum ratings, and avoid excessive heat generation within the resistor.
      • Using the normal maximum charge or discharge current, the sense resistor = 200 mV / 40.0 A = 5-mΩ maximum.
      • Considering a short circuit discharge current of 80 A, the recommended maximum SRP, SRN voltage of ≈0.75 V, and the maximum SCD threshold of 500 mV, the sense resistor should be below 500 mV / 80 A= 6.25-mΩ maximum.
    • Further tolerance analysis (value tolerance, temperature variation, and so on) and PCB design margin should also be considered, so a sense resistor of 1 mΩ is suitable with a 50-ppm temperature coefficient and power rating of 1 W.
  • The REGOUT is selected to provide the supply for an external host processor and the pullup supply for the I2C bus and ALERT pin, with output voltage selected for 3.3 V.
    • A 1 μF or larger capacitor should be placed at the REGOUT pin.
    • The REGOUT draws its input current from the REGSRC pin. This pin is connected to PACK+ through a series diode and 10 Ω resistor, with a 1-μF capacitor to VSS placed at the REGSRC pin.