JAJSS72 November   2023 BQ76907

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information bq76907
    5. 6.5  Supply Current
    6. 6.6  Digital I/O
    7. 6.7  REGOUT LDO
    8. 6.8  Voltage References
    9. 6.9  Coulomb Counter
    10. 6.10 Coulomb Counter Digital Filter
    11. 6.11 Current Wake Detector
    12. 6.12 Analog-to-Digital Converter
    13. 6.13 Cell Balancing
    14. 6.14 Internal Temperature Sensor
    15. 6.15 Thermistor Measurement
    16. 6.16 Hardware Overtemperature Detector
    17. 6.17 Internal Oscillator
    18. 6.18 Charge and Discharge FET Drivers
    19. 6.19 Comparator-Based Protection Subsystem
    20. 6.20 Timing Requirements - I2C Interface, 100kHz Mode
    21. 6.21 Timing Requirements - I2C Interface, 400kHz Mode
    22. 6.22 Timing Diagram
    23. 6.23 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Configuration
      1. 7.3.1 Commands and Subcommands
      2. 7.3.2 Configuration Using OTP or Registers
      3. 7.3.3 Device Security
    4. 7.4 Device Hardware Features
      1. 7.4.1  Voltage ADC
      2. 7.4.2  Coulomb Counter and Digital Filters
      3. 7.4.3  Protection FET Drivers
      4. 7.4.4  Voltage References
      5. 7.4.5  Multiplexer
      6. 7.4.6  LDOs
      7. 7.4.7  Standalone Versus Host Interface
      8. 7.4.8  ALERT Pin Operation
      9. 7.4.9  Low Frequency Oscillator
      10. 7.4.10 I2C Serial Communications Interface
    5. 7.5 Measurement Subsystem
      1. 7.5.1 Voltage Measurement
        1. 7.5.1.1 Voltage ADC Scheduling
        2. 7.5.1.2 Unused VC Pins
        3. 7.5.1.3 General Purpose ADCIN Functionality
      2. 7.5.2 Current Measurement and Charge Integration
      3. 7.5.3 Internal Temperature Measurement
      4. 7.5.4 Thermistor Temperature Measurement
      5. 7.5.5 Factory Trim and Calibration
    6. 7.6 Protection Subsystem
      1. 7.6.1 Protections Overview
      2. 7.6.2 Primary Protections
      3. 7.6.3 CHG Detector
      4. 7.6.4 Cell Open-Wire Protection
      5. 7.6.5 Diagnostic Checks
    7. 7.7 Cell Balancing
    8. 7.8 Device Operational Modes
      1. 7.8.1 Overview of Operational Modes
      2. 7.8.2 NORMAL Mode
      3. 7.8.3 SLEEP Mode
      4. 7.8.4 DEEPSLEEP Mode
      5. 7.8.5 SHUTDOWN Mode
      6. 7.8.6 CONFIG_UPDATE Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plot
      4. 8.2.4 Random Cell Connection Support
      5. 8.2.5 Startup Timing
      6. 8.2.6 FET Driver Turn-Off
      7. 8.2.7 Usage of Unused Pins
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Introduction to Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.5 Startup Timing

At initial power up of the BQ76907 device from a SHUTDOWN state, the device progresses through a sequence of events before entering NORMAL mode operation. These are described in Table 8-2 for an example configuration, with approximate timing shown.

Table 8-2 Startup Sequence and Timing
Step Comment Approximate Time (relative to wakeup event)
Wakeup event Either the TS pin or the VC0 pin is pulled up, triggering the device to exit SHUTDOWN mode. 0
REGOUT powered Measured with the OTP programmed to autonomously power the REGOUT LDO. 2.6 ms
First Cell-1 measurement completed Data from first measurement of Cell-1 can be read back. 3.2 ms
INITCOMP, ADSCAN, and FULLSCAN asserted (7s) These three signals are asserted together when the first startup sequence completes (measured with OTP programmed for them to appear on ALERT). [CVADCSPEED1:0] = 0x0, [IADCSPEED1:0] = 0x0, [SSADCSPEED1:0] = 0x0. 9.4 ms
FETs enabled (7s) Measured with the OTP programmed to autonomously enable FETs. [CVADCSPEED1:0] = 0x0, [IADCSPEED1:0] = 0x0, [SSADCSPEED1:0] = 0x0. 9.4 ms
INITCOMP, ADSCAN, and FULLSCAN asserted (5s) These three signals are asserted together when the first startup sequence completes (measured with OTP programmed for them to appear on ALERT). [CVADCSPEED1:0] = 0x0, [IADCSPEED1:0] = 0x0, [SSADCSPEED1:0] = 0x0. 8.6 ms
FETs enabled (5s) Measured with the OTP programmed to autonomously enable FETs. [CVADCSPEED1:0] = 0x0, [IADCSPEED1:0] = 0x0, [SSADCSPEED1:0] = 0x0. 8.6 ms

Figure 8-5 shows an example of an oscilloscope plot of a startup sequence with the device configured in OTP for a 5s pack, with [FET_EN] = 1 for autonomous FET control and providing the [INITCOMP] flag on the ALERT pin. The TS pin is pulled up to initiate device wakeup from SHUTDOWN.

GUID-ED029695-520C-41C5-AEA0-E8B58BA89236-low.png Figure 8-5 Startup Sequence for 5s pack with the [INITCOMP] Flag Displayed on the ALERT Pin (TS pin voltage in blue, DSG pin voltage shown in green)