JAJSS72 November   2023 BQ76907

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information bq76907
    5. 6.5  Supply Current
    6. 6.6  Digital I/O
    7. 6.7  REGOUT LDO
    8. 6.8  Voltage References
    9. 6.9  Coulomb Counter
    10. 6.10 Coulomb Counter Digital Filter
    11. 6.11 Current Wake Detector
    12. 6.12 Analog-to-Digital Converter
    13. 6.13 Cell Balancing
    14. 6.14 Internal Temperature Sensor
    15. 6.15 Thermistor Measurement
    16. 6.16 Hardware Overtemperature Detector
    17. 6.17 Internal Oscillator
    18. 6.18 Charge and Discharge FET Drivers
    19. 6.19 Comparator-Based Protection Subsystem
    20. 6.20 Timing Requirements - I2C Interface, 100kHz Mode
    21. 6.21 Timing Requirements - I2C Interface, 400kHz Mode
    22. 6.22 Timing Diagram
    23. 6.23 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Configuration
      1. 7.3.1 Commands and Subcommands
      2. 7.3.2 Configuration Using OTP or Registers
      3. 7.3.3 Device Security
    4. 7.4 Device Hardware Features
      1. 7.4.1  Voltage ADC
      2. 7.4.2  Coulomb Counter and Digital Filters
      3. 7.4.3  Protection FET Drivers
      4. 7.4.4  Voltage References
      5. 7.4.5  Multiplexer
      6. 7.4.6  LDOs
      7. 7.4.7  Standalone Versus Host Interface
      8. 7.4.8  ALERT Pin Operation
      9. 7.4.9  Low Frequency Oscillator
      10. 7.4.10 I2C Serial Communications Interface
    5. 7.5 Measurement Subsystem
      1. 7.5.1 Voltage Measurement
        1. 7.5.1.1 Voltage ADC Scheduling
        2. 7.5.1.2 Unused VC Pins
        3. 7.5.1.3 General Purpose ADCIN Functionality
      2. 7.5.2 Current Measurement and Charge Integration
      3. 7.5.3 Internal Temperature Measurement
      4. 7.5.4 Thermistor Temperature Measurement
      5. 7.5.5 Factory Trim and Calibration
    6. 7.6 Protection Subsystem
      1. 7.6.1 Protections Overview
      2. 7.6.2 Primary Protections
      3. 7.6.3 CHG Detector
      4. 7.6.4 Cell Open-Wire Protection
      5. 7.6.5 Diagnostic Checks
    7. 7.7 Cell Balancing
    8. 7.8 Device Operational Modes
      1. 7.8.1 Overview of Operational Modes
      2. 7.8.2 NORMAL Mode
      3. 7.8.3 SLEEP Mode
      4. 7.8.4 DEEPSLEEP Mode
      5. 7.8.5 SHUTDOWN Mode
      6. 7.8.6 CONFIG_UPDATE Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plot
      4. 8.2.4 Random Cell Connection Support
      5. 8.2.5 Startup Timing
      6. 8.2.6 FET Driver Turn-Off
      7. 8.2.7 Usage of Unused Pins
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Introduction to Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.18 Charge and Discharge FET Drivers

Typical values stated where TA = 25°C and VBAT = 25.9 V, min/max values stated where TA = -40°C to 110°C and VBAT = 3 V to 38.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(FETON_DSG) DSG driver enabled VREGSRC ≥ 12 V, CL= 20 nF 10.5 11.5 13 V
V(FETON_CHG) CHG driver enabled VREGSRC ≥ 12 V, CL= 20 nF 10 11 12 V
V(FETON_LOBAT_DSG) DSG driver enabled VREGSRC < 12 V, CL = 20 nF VREGSRC – 1 VREGSRC V
V(FETON_LOBAT_CHG) CHG driver enabled VREGSRC < 12 V, CL = 20 nF VREGSRC – 1.75 VREGSRC V
t(CHG_ON) CHG FET driver rise time CHG CL = 20 nF, RGATE = 100 Ω, VREGSRC = 12 V, 0.5 V to 5 V 50 85 µs
t(DSG_ON) DSG FET driver rise time DSG CL = 20 nF, RGATE = 100 Ω, VREGSRC = 12 V, 0.5 V to 5 V 35 55 µs
t(CHG_OFF) CHG FET driver fall time CHG CL = 20 nF, RGATE = 100 Ω, VREGSRC = 12 V, 80% to 20% of V(FETON_CHG) 24 35 µs
t(DSG_OFF) DSG FET driver fall time DSG CL = 20 nF, RGATE = 100 Ω, VREGSRC = 12 V, 80% to 20% of V(FETON_DSG) 2 3 µs
I(CHG_ON) CHG FET driver output current CHG enabled and pin held at 8 V, VREGSRC = 12 V 1 mA
I(DSG_ON) DSG FET driver output current DSG enabled and pin held at 8 V, VREGSRC = 12 V 1.56 mA
R(DSG_OFF) DSG FET driver off resistance DSG off and pin held at 100 mV 15 30 Ω
V(CHG_DETECT) CHG detector threshold CHG pin voltage rising 1.2 1.8 V
V(CHG_DET_HYS) CHG detector hysteresis 0.95 V