JAJSH19I October 2013 – March 2022 BQ76920 , BQ76930 , BQ76940
PRODMIX
VC1_HI, _LO (0x0C–0x0D), VC2_HI, _LO (0x0E–0x0F), VC3_HI, _LO (0x10–0x11), VC4_HI, _LO (0x12–0x13), VC5_HI, _LO (0x14–0x15) / BQ76930, BQ76940: VC6_HI, _LO (0x16–0x17), VC7_HI, _LO (0x18–0x19), VC8_HI, _LO (0x1A–0x1B), VC9_HI, _LO (0x1C–0x1D), VC10_HI, _LO (0x1E–0x1F) / BQ76940: VC11_HI, _LO (0x20–0x21), VC12_HI, _LO (0x22–0x23), VC13_HI, _LO (0x24–0x25), VC14_HI, _LO (0x26–0x27), VC15_HI, _LO (0x28–0x29) | ||||||||
---|---|---|---|---|---|---|---|---|
BIT | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NAME | — | — | D13 | D12 | D11 | D10 | D9 | D8 |
RESET | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
NAME | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
RESET | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
D11:8 (Bits 3–0): Cell “x” ADC reading, upper 6 MSB. Always returned as an atomic value if both high and low registers are read in the same transaction (using address auto-increment). | ||||
D7:0 (Bits 7–0): Cell ”x” ADC reading, lower 8 LSB. |
BIT | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|
NAME | D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
RESET | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
NAME | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
RESET | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
D15:8 (Bits 7–0): BAT calculation based on adding up Cells 1–15, upper 8 MSB. Always returned as an atomic value if both high and low registers are read in the same transaction (using address auto-increment). | ||||
D7:0 (Bits 7–0): BAT calculation based on adding up Cells 1–15, lower 8 LSB | ||||
BIT | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|
NAME | — | — | D13 | D12 | D11 | D10 | D9 | D8 |
RESET | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
NAME | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
RESET | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
D11:8 (Bits 3–0): TS1 or DIETEMP ADC reading, upper 6 MSB. Always returned as an atomic value if both high and low registers are read in the same transaction (using address auto-increment). | ||||
D7:0 (Bits 7–0): TS1 or DIETEMP ADC reading, lower 8 LSB |
BIT | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|
NAME | — | — | D13 | D12 | D11 | D10 | D9 | D8 |
RESET | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
NAME | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
RESET | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
D11:8 (Bits 3–0): TS2 ADC reading, upper 6 MSB. Always returned as an atomic value if both high and low registers are read in the same transaction (using address auto-increment). | ||||
D7:0 (Bits 7–0): TS2 ADC reading, lower 8 LSB |
BIT | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|
NAME | — | — | D13 | D12 | D11 | D10 | D9 | D8 |
RESET | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
NAME | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
RESET | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
D11:8 (Bits 3–0): TS3 ADC reading, upper 6 MSB. Always returned as an atomic value if both high and low registers are read in the same transaction (using address auto-increment). | ||||
D7:0 (Bits 7–0): TS3 ADC reading, lower 8 LSB |
BIT | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|
NAME | CC15 | CC14 | CC13 | CC12 | CC11 | CC10 | CC9 | CC8 |
RESET | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
NAME | CC7 | CC6 | CC5 | CC4 | CC3 | CC2 | CC1 | CC0 |
RESET | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
CC15:8 (Bits 7–0): Coulomb counter upper 8 MSB. Always returned as an atomic value if both high and low registers are read in the same transaction (using address auto-increment). | ||||
CC7:0 (Bits 7–0): Coulomb counter lower 8 LSB |
BIT | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|
NAME | — | — | — | — | ADCGAIN4 | ADCGAIN3 | — | — |
RESET | — | — | — | — | — | — | — | — |
ACCESS | R | R | R | R | R | R | R | R |
BIT | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|
NAME | ADCGAIN2 | ADCGAIN1 | ADCGAIN0 | — | — | — | — | — |
RESET | — | — | — | — | — | — | — | — |
ACCESS | R | R | R | R | R | R | R | R |
ADCGAIN4:3 (Bits 3–2, address 0x50): | ||||
ADC GAIN offset upper 2 MSB | ||||
ADCGAIN2:0 (Bits 7–5, address 0x59): | ||||
ADC GAIN offset lower 3 LSB | ||||
ADCGAIN<4:0> is a production-trimmed value for the ADC transfer function, in units of µV/LSB. The range is 365 µV/LSB to 396 µV/LSB, in steps of 1 µV/LSB, and may be calculated as follows: | ||||
GAIN = 365 µV/LSB + (ADCGAIN<4:0>in decimal) × (1 µV/LSB) | ||||
Alternately, a conversion table is provided below: |
ADC GAIN | Gain (µV/LSB) | ADC GAIN | Gain (µV/LSB) |
---|---|---|---|
0x00 | 365 | 0x10 | 381 |
0x01 | 366 | 0x11 | 382 |
0x02 | 367 | 0x12 | 383 |
0x03 | 368 | 0x13 | 384 |
0x04 | 369 | 0x14 | 385 |
0x05 | 370 | 0x15 | 386 |
0x06 | 371 | 0x16 | 387 |
0x07 | 372 | 0x17 | 388 |
0x08 | 373 | 0x18 | 389 |
0x09 | 374 | 0x19 | 390 |
0x0A | 375 | 0x1A | 391 |
0x0B | 376 | 0x1B | 392 |
0x0C | 377 | 0x1C | 393 |
0x0D | 378 | 0x1D | 394 |
0x0E | 379 | 0x1E | 395 |
0x0F | 380 | 0x1F | 396 |
BIT | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|
NAME | ADC OFFSET7 | ADC OFFSET6 | ADC OFFSET5 | ADC OFFSET4 | ADC OFFSET3 | ADC OFFSET2 | ADC OFFSET1 | ADC OFFSET0 |
RESET | — | — | — | — | — | — | — | — |
ACCESS | R | R | R | R | R | R | R | R |
ADCOFFSET7:0 (Bits 7–0): | ||||
ADC offset, stored in 2’s complement format in mV units. Positive full-scale range corresponds to 0x7F and negative full-scale corresponds to 0x80. The full-scale input range is –128 mV to 127 mV, with an LSB of 1 mV. | ||||
The table below shows example offsets. |
ADCOFFSET | Offset (mV) |
---|---|
0x00 | 0 |
0x01 | 1 |
0x7F | 127 |
0x80 | –128 |
0x81 | –127 |
0xFF | –1 |