JAJSKM2B December   2020  – December 2021 BQ76942

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information BQ76942
    5. 7.5  Supply Current
    6. 7.6  Digital I/O
    7. 7.7  LD Pin
    8. 7.8  Precharge (PCHG) and Predischarge (PDSG) FET Drive
    9. 7.9  FUSE Pin Functionality
    10. 7.10 REG18 LDO
    11. 7.11 REG0 Pre-regulator
    12. 7.12 REG1 LDO
    13. 7.13 REG2 LDO
    14. 7.14 Voltage References
    15. 7.15 Coulomb Counter
    16. 7.16 Coulomb Counter Digital Filter (CC1)
    17. 7.17 Current Measurement Digital Filter (CC2)
    18. 7.18 Current Wake Detector
    19. 7.19 Analog-to-Digital Converter
    20. 7.20 Cell Balancing
    21. 7.21 Cell Open Wire Detector
    22. 7.22 Internal Temperature Sensor
    23. 7.23 Thermistor Measurement
    24. 7.24 Internal Oscillators
    25. 7.25 High-Side NFET Drivers
    26. 7.26 Comparator-Based Protection Subsystem
    27. 7.27 Timing Requirements – I2C Interface, 100kHz Mode
    28. 7.28 Timing Requirements – I2C Interface, 400kHz Mode
    29. 7.29 Timing Requirements – HDQ Interface
    30. 7.30 Timing Requirements – SPI Interface
    31. 7.31 Interface Timing Diagrams
    32. 7.32 Typical Characteristics
  8. 8 Device Description
    1. 8.1 Overview
    2. 8.2 BQ76942 Device Versions
    3. 8.3 Functional Block Diagram
    4. 8.4 Diagnostics
  9. 9 Device Configuration
    1. 9.1 Commands and Subcommands
    2. 9.2 Configuration Using OTP or Registers
    3. 9.3 Device Security
    4. 9.4 Scratchpad Memory
  10. 10Measurement Subsystem
    1. 10.1  Voltage Measurement
      1. 10.1.1 Voltage Measurement Schedule
      2. 10.1.2 Usage of VC Pins for Cells Versus Interconnect
      3. 10.1.3 Cell 1 Voltage Validation During SLEEP Mode
    2. 10.2  General Purpose ADCIN Functionality
    3. 10.3  Coulomb Counter and Digital Filters
    4. 10.4  Synchronized Voltage and Current Measurement
    5. 10.5  Internal Temperature Measurement
    6. 10.6  Thermistor Temperature Measurement
    7. 10.7  Factory Trim of Voltage ADC
    8. 10.8  Voltage Calibration (ADC Measurements)
    9. 10.9  Voltage Calibration (COV and CUV Protections)
    10. 10.10 Current Calibration
    11. 10.11 Temperature Calibration
  11. 11Primary and Secondary Protection Subsystems
    1. 11.1 Protections Overview
    2. 11.2 Primary Protections
    3. 11.3 Secondary Protections
    4. 11.4 High-Side NFET Drivers
    5. 11.5 Protection FETs Configuration and Control
      1. 11.5.1 FET Configuration
      2. 11.5.2 PRECHARGE and PREDISCHARGE Modes
    6. 11.6 Load Detect Functionality
  12. 12Device Hardware Features
    1. 12.1  Voltage References
    2. 12.2  ADC Multiplexer
    3. 12.3  LDOs
      1. 12.3.1 Preregulator Control
      2. 12.3.2 REG1 and REG2 LDO Controls
    4. 12.4  Standalone Versus Host Interface
    5. 12.5  Multifunction Pin Controls
    6. 12.6  RST_SHUT Pin Operation
    7. 12.7  CFETOFF, DFETOFF, BOTHOFF Pin Functionality
    8. 12.8  ALERT Pin Operation
    9. 12.9  DDSG and DCHG Pin Operation
    10. 12.10 Fuse Drive
    11. 12.11 Cell Open Wire
    12. 12.12 Low Frequency Oscillator
    13. 12.13 High Frequency Oscillator
  13. 13Device Functional Modes
    1. 13.1 Overview
    2. 13.2 NORMAL Mode
    3. 13.3 SLEEP Mode
    4. 13.4 DEEPSLEEP Mode
    5. 13.5 SHUTDOWN Mode
    6. 13.6 CONFIG_UPDATE Mode
  14. 14Serial Communications Interface
    1. 14.1 Serial Communications Overview
    2. 14.2 I2C Communications Subsystem
    3. 14.3 SPI Communications Interface
      1. 14.3.1 SPI Protocol
    4. 14.4 HDQ Communications Interface
  15. 15Cell Balancing
    1. 15.1 Cell Balancing Overview
  16. 16Application and Implementation
    1. 16.1 Application Information
    2. 16.2 Typical Applications
      1. 16.2.1 Design Requirements (Example)
      2. 16.2.2 Detailed Design Procedure
      3. 16.2.3 Application Performance Plot
      4. 16.2.4 Calibration Process
      5. 16.2.5 Design Example
    3. 16.3 Random Cell Connection Support
    4. 16.4 Startup Timing
    5. 16.5 FET Driver Turn-Off
    6. 16.6 Unused Pins
  17. 17Power Supply Requirements
  18. 18Layout
    1. 18.1 Layout Guidelines
    2. 18.2 Layout Example
  19. 19Device and Documentation Support
    1. 19.1 Third-Party Products Disclaimer
    2. 19.2 Documentation Support
      1. 19.2.1 Receiving Notification of Documentation Updates
    3. 19.3 サポート・リソース
    4. 19.4 Trademarks
    5. 19.5 Electrostatic Discharge Caution
    6. 19.6 Glossary
  20. 20Mechanical, Packaging, Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

Figure 6-1 Pinout (top)
Table 6-1 BQ76942 TQFP Package (PFB) Pin Functions
PIN I/O TYPE DESCRIPTION
NO. NAME
1 NC — — This pin is not connected to silicon.
2 VC9 I IA Sense voltage input pin for the ninth cell from the bottom of the stack, balance current input for the ninth cell from the bottom of the stack, and return balance current for the tenth cell from the bottom of the stack
3 NC — — This pin is not connected to silicon.
4 VC8 I IA Sense voltage input pin for the eighth cell from the bottom of the stack, balance current input for the eighth cell from the bottom of the stack, and return balance current for the ninth cell from the bottom of the stack
5 NC — — This pin is not connected to silicon.
6 VC7 I IA Sense voltage input pin for the seventh cell from the bottom of the stack, balance current input for the seventh cell from the bottom of the stack and return balance current for the eighth cell from the bottom of the stack
7 NC — — This pin is not connected to silicon.
8 VC6 I IA Sense voltage input pin for the sixth cell from the bottom of the stack, balance current input for the sixth cell from the bottom of the stack, and return balance current for the seventh cell from the bottom of the stack
9 NC — — This pin is not connected to silicon.
10 VC5 I IA Sense voltage input pin for the fifth cell from the bottom of the stack, balance current input for the fifth cell from the bottom of the stack, and return balance current for the sixth cell from the bottom of the stack
11 NC — — This pin is not connected to silicon.
12 VC4 I IA Sense voltage input pin for the fourth cell from the bottom of the stack, balance current input for the fourth cell from the bottom of the stack, and return balance current for the fifth cell from the bottom of the stack
13 VC3 I IA Sense voltage input pin for the third cell from the bottom of the stack, balance current input for the third cell from the bottom of the stack, and return balance current for the fourth cell from the bottom of the stack
14 VC2 I IA Sense voltage input pin for the second cell from the bottom of the stack, balance current input for the second cell from the bottom of the stack, and return balance current for the third cell from the bottom of the stack
15 VC1 I IA Sense voltage input pin for the first cell from the bottom of the stack, balance current input for the first cell from the bottom of the stack, and return balance current for the second cell from the bottom of the stack
16 VC0 I IA Sense voltage input pin for negative terminal of the first cell from the bottom of the stack, and return balance current for first cell from the bottom of the stack
17 VSS — P Device ground
18 SRP I IA Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN, where SRP is the top of the sense resistor. A charging current generates a positive voltage at SRP relative to SRN.
19 NC — — This pin is not connected to silicon.
20 SRN I IA Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN, where SRN is the bottom of the sense resistor. A charging current generates a positive voltage at SRP relative to SRN.
21 TS1 I/O OD, I/OA Thermistor input, or general purpose ADC input
22 TS2 I/O OD, I/OA Thermistor input and functions as wakeup from SHUTDOWN, or general purpose ADC input
23 TS3 I/O OD, I/OA Thermistor input, or general purpose ADC input
24 REG18 O P Internal 1.8 V-LDO output (only for internal use)
25 ALERT I/O I/OD, I/OA Multifunction pin, can be ALERT output, or HDQ I/O, or thermistor input, or general purpose ADC input, or general purpose digital output
26 SCL I/O I/OD Multifunction pin, can be SCL or SPI_SCLK
27 SDA I/O I/OD Multifunction pin, can be SDA or SPI_MISO
28 HDQ I/O I/OD, I/OA Multifunction pin, can be HDQ I/O, or SPI_MOSI, or thermistor input, or general purpose ADC input, or general purpose digital output
29 CFETOFF I/O I/OD, I/OA Multifunction pin, can be CFETOFF, or SPI_CS, or thermistor input, or general purpose ADC input, or general purpose digital output
30 DFETOFF I/O I/OD, I/OA Multifunction pin, can be DFETOFF or BOTHOFF, or thermistor input, or general purpose ADC input, or general purpose digital output
31 DCHG I/O OD, I/OA Multifunction pin, can be DCHG, or thermistor input, or general purpose ADC input, or general purpose digital output
32 DDSG I/O OD, I/OA Multifunction pin, can be DDSG, or thermistor input, or general purpose ADC input, or general purpose digital output
33 RST_SHUT I ID Digital input pin for reset or shutdown
34 REG2 O P Second LDO (REG2) output, which can be programmed for 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V
35 REG1 O P First LDO (REG1) output, which can be programmed for 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V
36 REGIN I IA Input pin for REG1 and REG2 LDOs
37 BREG O OA Base control signal for external preregulator transistor
38 FUSE I/O I/OA Fuse sense and drive
39 PDSG O OA Predischarge PFET control
40 PCHG O OA Precharge PFET control
41 LD I/O I/OA Load detect pin
42 PACK I IA Pack sense input pin
43 DSG O OA NMOS discharge FET drive output pin
44 NC — — This pin is not connected to silicon.
45 CHG O OA NMOS charge FET drive output pin
46 CP1 I/O I/OA Charge pump capacitor
47 BAT I P Primary power supply input pin
48 VC10 I IA Sense voltage input pin for the tenth cell from the bottom of the stack, balance current input for the tenth cell from the bottom of the stack, and top-of-stack measurement point