1 |
NC |
— |
— |
This pin is not connected to silicon. |
2 |
VC9 |
I |
IA |
Sense voltage input pin for the ninth cell from the bottom of the
stack, balance current input for the ninth cell from the bottom of
the stack, and return balance current for the tenth cell from the
bottom of the
stack |
3 |
NC |
— |
— |
This pin is not connected to silicon. |
4 |
VC8 |
I |
IA |
Sense voltage input pin for the eighth cell from the bottom of the
stack, balance current input for the eighth cell from the bottom of
the stack, and return balance current for the ninth cell from the
bottom of the
stack |
5 |
NC |
— |
— |
This pin is not connected to silicon. |
6 |
VC7 |
I |
IA |
Sense voltage input pin for the seventh cell from the bottom of the
stack, balance current input for the seventh cell from the bottom of
the stack and return balance current for the eighth cell from the
bottom of the
stack |
7 |
NC |
— |
— |
This pin is not connected to silicon. |
8 |
VC6 |
I |
IA |
Sense voltage input pin for the sixth cell from the bottom of the
stack, balance current input for the sixth cell from the bottom of
the stack, and return balance current for the seventh cell from the
bottom of the
stack |
9 |
NC |
— |
— |
This pin is not connected to silicon. |
10 |
VC5 |
I |
IA |
Sense voltage input pin for the fifth cell from the bottom of the
stack, balance current input for the fifth cell from the bottom of
the stack, and return balance current for the sixth cell from the
bottom of the
stack |
11 |
NC |
— |
— |
This pin is not connected to silicon. |
12 |
VC4 |
I |
IA |
Sense voltage input pin for the fourth cell from the bottom of the
stack, balance current input for the fourth cell from the bottom of
the stack, and return balance current for the fifth cell from the
bottom of the
stack |
13 |
VC3 |
I |
IA |
Sense voltage input pin for the third cell from the bottom of the
stack, balance current input for the third cell from the bottom of
the stack, and return balance current for the fourth cell from the
bottom of the
stack |
14 |
VC2 |
I |
IA |
Sense voltage input pin for the second cell from the bottom of the
stack, balance current input for the second cell from the bottom of
the stack, and return balance current for the third cell from the
bottom of the
stack |
15 |
VC1 |
I |
IA |
Sense voltage input pin for the first cell from the bottom of the
stack, balance current input for the first cell from the bottom of
the stack, and return balance current for the second cell from the
bottom of the
stack |
16 |
VC0 |
I |
IA |
Sense voltage input pin for negative terminal of the first cell
from the bottom of the stack, and return balance current for first
cell from the bottom of the
stack |
17 |
VSS |
— |
P |
Device ground |
18 |
SRP |
I |
IA |
Analog input pin connected to the internal coulomb counter
peripheral for integrating a small voltage between SRP and SRN,
where SRP is the top of the sense resistor. A charging current
generates a positive voltage at SRP relative to SRN. |
19 |
NC |
— |
— |
This pin is not connected to silicon. |
20 |
SRN |
I |
IA |
Analog input pin connected to the internal coulomb counter
peripheral for integrating a small voltage between SRP and SRN,
where SRN is the bottom of the sense resistor. A charging current
generates a positive voltage at SRP relative to SRN. |
21 |
TS1 |
I/O |
OD, I/OA |
Thermistor input, or general purpose ADC
input |
22 |
TS2 |
I/O |
OD, I/OA |
Thermistor input and functions as wakeup from SHUTDOWN, or general
purpose ADC
input |
23 |
TS3 |
I/O |
OD, I/OA |
Thermistor input, or general purpose ADC
input |
24 |
REG18 |
O |
P |
Internal 1.8
V-LDO
output (only for internal
use) |
25 |
ALERT |
I/O |
I/OD, I/OA |
Multifunction pin, can be ALERT output, or HDQ I/O, or thermistor
input, or general purpose ADC input, or general purpose digital
output |
26 |
SCL |
I/O |
I/OD |
Multifunction pin, can be SCL or
SPI_SCLK |
27 |
SDA |
I/O |
I/OD |
Multifunction pin, can be SDA or
SPI_MISO |
28 |
HDQ |
I/O |
I/OD, I/OA |
Multifunction pin, can be HDQ I/O, or SPI_MOSI, or thermistor
input, or general purpose ADC input, or general purpose digital
output |
29 |
CFETOFF |
I/O |
I/OD, I/OA |
Multifunction pin, can be CFETOFF, or SPI_CS, or thermistor input,
or general purpose ADC input, or general purpose digital
output |
30 |
DFETOFF |
I/O |
I/OD, I/OA |
Multifunction pin, can be DFETOFF or BOTHOFF, or thermistor input,
or general purpose ADC input, or general purpose digital
output |
31 |
DCHG |
I/O |
OD, I/OA |
Multifunction pin, can be DCHG, or thermistor input, or general
purpose ADC input, or general purpose digital
output |
32 |
DDSG |
I/O |
OD, I/OA |
Multifunction pin, can be DDSG, or thermistor input, or general
purpose ADC input, or general purpose digital
output |
33 |
RST_SHUT |
I |
ID |
Digital input pin for reset or
shutdown |
34 |
REG2 |
O |
P |
Second LDO (REG2) output, which can be programmed for 1.8 V, 2.5 V,
3.0 V, 3.3 V,
or
5.0
V |
35 |
REG1 |
O |
P |
First LDO (REG1) output, which can be programmed for 1.8 V, 2.5 V,
3.0 V, 3.3 V,
or
5.0
V |
36 |
REGIN |
I |
IA |
Input pin for REG1 and REG2 LDOs |
37 |
BREG |
O |
OA |
Base control signal for external
preregulator
transistor |
38 |
FUSE |
I/O |
I/OA |
Fuse sense and drive |
39 |
PDSG |
O |
OA |
Predischarge PFET control |
40 |
PCHG |
O |
OA |
Precharge PFET control |
41 |
LD |
I/O |
I/OA |
Load detect pin |
42 |
PACK |
I |
IA |
Pack sense input pin |
43 |
DSG |
O |
OA |
NMOS
discharge
FET drive output pin |
44 |
NC |
— |
— |
This pin is not connected to silicon. |
45 |
CHG |
O |
OA |
NMOS
charge
FET drive output pin |
46 |
CP1 |
I/O |
I/OA |
Charge pump capacitor |
47 |
BAT |
I |
P |
Primary power supply input pin |
48 |
VC10 |
I |
IA |
Sense voltage input pin for the tenth cell from the bottom of the
stack, balance current input for the tenth cell from the bottom of
the stack, and top-of-stack measurement
point |