テキサス・インスツルメンツの BQ76942 は、3 直列~10 直列リチウムイオン、リチウムポリマー、LiFePO4 バッテリ・パック用の高集積高精度バッテリ・モニタおよびプロテクタです。このデバイスは
高精度の監視システム、高度に構成可能な保護サブシステム、自律制御またはホスト制御のセル・バランシング機能を内蔵しています。ハイサイド・チャージ・ポンプ NFET ドライバ、外部システム用のプログラム可能なデュアル LDO、400kHz I2C、SPI、HDQ 1 線式規格をサポートするホスト通信ペリフェラルも統合されています。BQ76942 は 48 ピン TQFP パッケージで供給されます。
部品番号(1) | パッケージ | 本体サイズ (公称) |
---|---|---|
BQ76942xx | PFB (48 ピン) | 7mm × 7mm |
Changes from Revision A (January 2021) to Revision B (December 2021)
Changes from Revision * (November 2020) to Revision A (January 2021)
BQ76942 Device Family | |||
---|---|---|---|
PART NUMBER | Communications Interface | CRC Enabled | REG1 LDO Default |
BQ76942 | I2C | N | Disabled |
BQ7694201 | SPI | Y | Disabled |
BQ7694202 | I2C | Y | Enabled, set to 3.3 V |
BQ7694203 | SPI | Y | Enabled, set to 5 V |
BQ7694204 | SPI | Y | Enabled, set to 3.3 V |
PIN | I/O | TYPE | DESCRIPTION | |
---|---|---|---|---|
NO. | NAME | |||
1 | NC | — | — | This pin is not connected to silicon. |
2 | VC9 | I | IA | Sense voltage input pin for the ninth cell from the bottom of the stack, balance current input for the ninth cell from the bottom of the stack, and return balance current for the tenth cell from the bottom of the stack |
3 | NC | — | — | This pin is not connected to silicon. |
4 | VC8 | I | IA | Sense voltage input pin for the eighth cell from the bottom of the stack, balance current input for the eighth cell from the bottom of the stack, and return balance current for the ninth cell from the bottom of the stack |
5 | NC | — | — | This pin is not connected to silicon. |
6 | VC7 | I | IA | Sense voltage input pin for the seventh cell from the bottom of the stack, balance current input for the seventh cell from the bottom of the stack and return balance current for the eighth cell from the bottom of the stack |
7 | NC | — | — | This pin is not connected to silicon. |
8 | VC6 | I | IA | Sense voltage input pin for the sixth cell from the bottom of the stack, balance current input for the sixth cell from the bottom of the stack, and return balance current for the seventh cell from the bottom of the stack |
9 | NC | — | — | This pin is not connected to silicon. |
10 | VC5 | I | IA | Sense voltage input pin for the fifth cell from the bottom of the stack, balance current input for the fifth cell from the bottom of the stack, and return balance current for the sixth cell from the bottom of the stack |
11 | NC | — | — | This pin is not connected to silicon. |
12 | VC4 | I | IA | Sense voltage input pin for the fourth cell from the bottom of the stack, balance current input for the fourth cell from the bottom of the stack, and return balance current for the fifth cell from the bottom of the stack |
13 | VC3 | I | IA | Sense voltage input pin for the third cell from the bottom of the stack, balance current input for the third cell from the bottom of the stack, and return balance current for the fourth cell from the bottom of the stack |
14 | VC2 | I | IA | Sense voltage input pin for the second cell from the bottom of the stack, balance current input for the second cell from the bottom of the stack, and return balance current for the third cell from the bottom of the stack |
15 | VC1 | I | IA | Sense voltage input pin for the first cell from the bottom of the stack, balance current input for the first cell from the bottom of the stack, and return balance current for the second cell from the bottom of the stack |
16 | VC0 | I | IA | Sense voltage input pin for negative terminal of the first cell from the bottom of the stack, and return balance current for first cell from the bottom of the stack |
17 | VSS | — | P | Device ground |
18 | SRP | I | IA | Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN, where SRP is the top of the sense resistor. A charging current generates a positive voltage at SRP relative to SRN. |
19 | NC | — | — | This pin is not connected to silicon. |
20 | SRN | I | IA | Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN, where SRN is the bottom of the sense resistor. A charging current generates a positive voltage at SRP relative to SRN. |
21 | TS1 | I/O | OD, I/OA | Thermistor input, or general purpose ADC input |
22 | TS2 | I/O | OD, I/OA | Thermistor input and functions as wakeup from SHUTDOWN, or general purpose ADC input |
23 | TS3 | I/O | OD, I/OA | Thermistor input, or general purpose ADC input |
24 | REG18 | O | P | Internal 1.8 V-LDO output (only for internal use) |
25 | ALERT | I/O | I/OD, I/OA | Multifunction pin, can be ALERT output, or HDQ I/O, or thermistor input, or general purpose ADC input, or general purpose digital output |
26 | SCL | I/O | I/OD | Multifunction pin, can be SCL or SPI_SCLK |
27 | SDA | I/O | I/OD | Multifunction pin, can be SDA or SPI_MISO |
28 | HDQ | I/O | I/OD, I/OA | Multifunction pin, can be HDQ I/O, or SPI_MOSI, or thermistor input, or general purpose ADC input, or general purpose digital output |
29 | CFETOFF | I/O | I/OD, I/OA | Multifunction pin, can be CFETOFF, or SPI_CS, or thermistor input, or general purpose ADC input, or general purpose digital output |
30 | DFETOFF | I/O | I/OD, I/OA | Multifunction pin, can be DFETOFF or BOTHOFF, or thermistor input, or general purpose ADC input, or general purpose digital output |
31 | DCHG | I/O | OD, I/OA | Multifunction pin, can be DCHG, or thermistor input, or general purpose ADC input, or general purpose digital output |
32 | DDSG | I/O | OD, I/OA | Multifunction pin, can be DDSG, or thermistor input, or general purpose ADC input, or general purpose digital output |
33 | RST_SHUT | I | ID | Digital input pin for reset or shutdown |
34 | REG2 | O | P | Second LDO (REG2) output, which can be programmed for 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V |
35 | REG1 | O | P | First LDO (REG1) output, which can be programmed for 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V |
36 | REGIN | I | IA | Input pin for REG1 and REG2 LDOs |
37 | BREG | O | OA | Base control signal for external preregulator transistor |
38 | FUSE | I/O | I/OA | Fuse sense and drive |
39 | PDSG | O | OA | Predischarge PFET control |
40 | PCHG | O | OA | Precharge PFET control |
41 | LD | I/O | I/OA | Load detect pin |
42 | PACK | I | IA | Pack sense input pin |
43 | DSG | O | OA | NMOS discharge FET drive output pin |
44 | NC | — | — | This pin is not connected to silicon. |
45 | CHG | O | OA | NMOS charge FET drive output pin |
46 | CP1 | I/O | I/OA | Charge pump capacitor |
47 | BAT | I | P | Primary power supply input pin |
48 | VC10 | I | IA | Sense voltage input pin for the tenth cell from the bottom of the stack, balance current input for the tenth cell from the bottom of the stack, and top-of-stack measurement point |
DESCRIPTION | PINS | MIN | MAX | UNIT |
---|---|---|---|---|
Supply voltage range | BAT | VSS–0.3 | VSS+85 | V |
Input voltage range, VIN | PACK, LD | VSS–0.3 | VSS+85 | V |
Input voltage range, VIN | PACK, PCHG, PDSG, LD | the maximum of VBAT–10 or VLD–10 | VSS+85 | V |
Input voltage range, VIN | REGIN | the maximum of VSS–0.3 or VBREG–5.5 | the minimum of VSS+6 or VBAT+0.3 or VBREG+0.3 | V |
Input voltage range, VIN | FUSE(2) | VSS–0.3 | the minimum of VSS+20 or VBAT+0.3 | V |
Input voltage range, VIN | BREG | the maximum of VSS–0.3 or VREGIN–0.3 | VREGIN+5.5 | V |
Input voltage range, VIN | REG1, REG2 | VSS–0.3 | minimum of VSS+6 or VREGIN+0.3 | V |
Input voltage range, VIN | ALERT, SCL, SDA, HDQ, CFETOFF, DFETOFF, DCHG, DDSG, RST_SHUT (3) | VSS–0.3 | VSS+6 | V |
Input voltage range, VIN | TS1, TS2, TS3, ALERT, CFETOFF, DFETOFF, HDQ, DCHG, DDSG (when used as thermistor or general purpose ADC input) | VSS–0.3 | VREG18 + 0.3 | V |
Input voltage range, VIN | SRP, SRN | VSS–0.3 | VREG18 + 0.3 | V |
Input voltage range, VIN | VC10 | maximum of VSS–0.3 and VC9–0.3 | VSS+85 | V |
Input voltage range, VIN | VC9 | maximum of VSS–0.3 and VC8–0.3 | VSS+85 | V |
Input voltage range, VIN | VC8 | maximum of VSS–0.3 and VC7–0.3 | VSS+85 | V |
Input voltage range, VIN | VC7 | maximum of VSS–0.3 and VC6–0.3 | VSS+85 | V |
Input voltage range, VIN | VC6 | maximum of VSS–0.3 and VC5–0.3 | VSS+85 | V |
Input voltage range, VIN | VC5 | maximum of VSS–0.3 and VC4–0.3 | VSS+85 | V |
Input voltage range, VIN | VC4 | maximum of VSS–0.3 and VC3–0.3 | VSS+85 | V |
Input voltage range, VIN | VC3 | maximum of VSS–0.3 and VC2–0.3 | VSS+85 | V |
Input voltage range, VIN | VC2 | maximum of VSS–0.3 and VC1–0.3 | VSS+85 | V |
Input voltage range, VIN | VC1 | maximum of VSS–0.3 and VC0–0.3 | VSS+85 | V |
Input voltage range, VIN | VC0 | VSS–0.3 | VSS+6 | V |
Output voltage range, VO | CP1 | VBAT–0.3 | the minimum of VSS+85 or VBAT+15 | V |
Output voltage range, VO | CHG | VSS–0.3 | VSS+85 | V |
Output voltage range, VO | DSG | VSS–0.3 | VSS+85 | V |
Output voltage range, VO | REG1, REG2, TS2 (for wakeup function), ALERT, CFETOFF, DFETOFF, HDQ, DCHG, DDSG, when configured to drive a digital output | VSS–0.3 | VSS+6 | V |
Output voltage range, VO | REG18 | VSS–0.3 | VSS+2 | V |
Maximum cell balancing current through a single cell | VC0 – VC10 | 100 | mA | |
Maximum VSS current, ISS | 75 | mA | ||
Functional temperature, TFUNC | –40 | 85 | °C | |
Junction temperature, TJ | –55 | 150 | °C | |
Storage temperature, TSTG | –55 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±1000 | V |
V(ESD) | Electrostatic discharge | Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2) | ±250 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VBAT | Supply voltage | Voltage on BAT pin (normal operation) | 4.7 | 55 | V | |
VBAT | Supply voltage(3) | Voltage on BAT pin (OTP programming) | 10 | 12 | V | |
TOTP | OTP programming temperature(3) | –40 | 45 | °C | ||
VPORA | Power-on reset | Rising threshold on BAT | 3 | 4 | V | |
VPORA_HYS | Power-on reset hysteresis | Device shuts down when BAT < VPORA - VPORA_HYS | 180 | mV | ||
VWAKEONLD | Wake on LD voltage | Rising edge on LD, with BAT already in valid range | 0.8 | 1.45 | 2.25 | V |
VWAKEONTS2 | Wake on TS2 voltage | Falling edge on TS2, with BAT already in valid range. TS2 will be weakly driven with a 5 V level during shutdown. | 0.7 | 1.1 | V | |
VIN | Input voltage range(3) | PACK, LD | 0 | 55 | V | |
VIN | Input voltage range(3) | PCHG, PDSG | the maximum of VBAT–9 or VLD–9 | 55 | V | |
VIN | Input voltage range(3) | REG1, REG2, RST_SHUT, ALERT, SCL, SDA, HDQ, CFETOFF, DFETOFF, DCHG, DDSG, except when the pin is being used for general purpose ADC input or thermistor measurement. | 0 | 5.5 | V | |
VIN | Input voltage range(3) | TS1, TS2, TS3, CFETOFF, DFETOFF, DCHG, DDSG, ALERT, HDQ, when the pin is configured for general purpose ADC input or thermistor measurement. | 0 | VREG18 | V | |
VIN | Input voltage range(5) | SRP, SRN, SRP-SRN (while measuring current) | –0.2 | 0.2 | V | |
VIN | Input voltage range(3) | SRP, SRN (without measuring current) | –0.2 | 0.75 | V | |
VIN | Input voltage range(3) (4) | VVC(0) | –0.2 | 0.5 | V | |
VIN | Input voltage range(5) | VVC(x), 1 ≤ x ≤ 4 | maximum of VVC(x–1) – 0.2 or VSS–0.2 | minimum of VVC(x–1)+5.5 or VSS+55 | V | |
VIN | Input voltage range | VVC(x), x ≥ 5 | maximum of VVC(x–1) – 0.2 or VSS + 2.0 | minimum of VVC(x–1) + 5.5 or VSS + 55 | V | |
RC | External cell input resistance(3) (6) | 20 | 100 | Ω | ||
RC | External cell input capacitance(3) (6) | 0.1 | 0.22 | 1 | µF | |
VO | Output voltage range | LD | 55 | V | ||
VO | Output voltage range(5) | CHG, DSG, CP1 | 70 | V | ||
TOPR | Operating temperature(5) | –40 | 85 | °C | ||
VCELL(ACC) | Cell voltage measurement accuracy | 2 V < VVC(x) - VVC(x-1) < 5 V, TA = 25°C, 1 ≤ x ≤ 10(1) (2) | –5 | 5 | mV | |
VCELL(ACC) | Cell voltage measurement accuracy(5) | 2 V < VVC(x) - VVC(x-1) < 5 V, TA = 0°C to 60°C, 1 ≤ x ≤ 10(1) (2) | –10 | 10 | mV | |
VCELL(ACC) | Cell voltage measurement accuracy(5) | –0.2 V < VVC(x) - VVC(x-1) < 5.5 V, TA = -40°C to 85°C, 1 ≤ x ≤ 10(1) (2) | –15 | 15 | mV | |
VSTACK(ACC) | Stack voltage (VC10 - VSS) measurement accuracy(5) | 0 V < VVC10 - VVSS ≤ 55 V, TA = -40°C to 85°C(1) | –0.5 | 0.5 | V | |
VPACK(ACC) | PACK pin voltage measurement accuracy(5) | 0 V < VPACK - VVSS ≤ 55 V, TA = -40°C to 85°C(1) | –0.5 | 0.5 | V | |
VLD(ACC) | LD pin voltage measurement accuracy(5) | 0 V < VLD - VVSS ≤ 55 V, TA = -40°C to 85°C(1) | –0.5 | 0.5 | V |
THERMAL METRIC(1) | BQ76942 | UNIT | |
---|---|---|---|
PFB (TQFP) | |||
48 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 66.0 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 19.6 | °C/W |
RθJB | Junction-to-board thermal resistance | 29.3 | °C/W |
ΨJT | Junction-to-top characterization parameter | 0.8 | °C/W |
ΨJB | Junction-to-board characterization parameter | 29.1 | °C/W |