JAJSSG6 December   2023 BQ76972

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information BQ76952
    5. 6.5  Supply Current
    6. 6.6  Digital I/O
    7. 6.7  LD Pin
    8. 6.8  Precharge (PCHG) and Predischarge (PDSG) FET Drive
    9. 6.9  FUSE Pin Functionality
    10. 6.10 REG18 LDO
    11. 6.11 REG0 Pre-regulator
    12. 6.12 REG1 LDO
    13. 6.13 REG2 LDO
    14. 6.14 Voltage References
    15. 6.15 Coulomb Counter
    16. 6.16 Coulomb Counter Digital Filter (CC1)
    17. 6.17 Current Measurement Digital Filter (CC2)
    18. 6.18 Current Wake Detector
    19. 6.19 Analog-to-Digital Converter
    20. 6.20 Cell Voltage Measurement Accuracy
    21. 6.21 Cell Balancing
    22. 6.22 Cell Open Wire Detector
    23. 6.23 Internal Temperature Sensor
    24. 6.24 Thermistor Measurement
    25. 6.25 Internal Oscillators
    26. 6.26 High-side NFET Drivers
    27. 6.27 Comparator-Based Protection Subsystem
    28. 6.28 Timing Requirements - I2C Interface, 100kHz Mode
    29. 6.29 Timing Requirements - I2C Interface, 400kHz Mode
    30. 6.30 Timing Requirements - HDQ Interface
    31. 6.31 Timing Requirements - SPI Interface
    32. 6.32 Interface Timing Diagrams
    33. 6.33 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  BQ76972 Device Versions
    4. 7.4  Diagnostics
    5. 7.5  Device Configuration
      1. 7.5.1 Commands and Subcommands
      2. 7.5.2 Configuration Using OTP or Registers
      3. 7.5.3 Device Security
      4. 7.5.4 Scratchpad Memory
    6. 7.6  Measurement Subsystem
      1. 7.6.1  Voltage Measurement
        1. 7.6.1.1 Voltage Measurement Schedule
        2. 7.6.1.2 Usage of VC Pins for Cells Versus Interconnect
        3. 7.6.1.3 Cell 1 Voltage Validation During SLEEP Mode
      2. 7.6.2  General Purpose ADCIN Functionality
      3. 7.6.3  Coulomb Counter and Digital Filters
      4. 7.6.4  Synchronized Voltage and Current Measurement
      5. 7.6.5  Internal Temperature Measurement
      6. 7.6.6  Thermistor Temperature Measurement
      7. 7.6.7  Factory Trim of Voltage ADC
      8. 7.6.8  Cell Voltage Measurement Accuracy
        1. 7.6.8.1 Fixed Offset Adjustment
        2. 7.6.8.2 Cell Offset Calibration
      9. 7.6.9  Voltage Calibration (ADC Measurements)
      10. 7.6.10 Voltage Calibration (COV and CUV Protections)
      11. 7.6.11 Current Calibration
      12. 7.6.12 Temperature Calibration
    7. 7.7  Primary and Secondary Protection Subsystems
      1. 7.7.1 Protections Overview
      2. 7.7.2 Primary Protections
      3. 7.7.3 Secondary Protections
      4. 7.7.4 High-Side NFET Drivers
      5. 7.7.5 Protection FETs Configuration and Control
        1. 7.7.5.1 FET Configuration
        2. 7.7.5.2 PRECHARGE and PREDISCHARGE Modes
      6. 7.7.6 Load Detect Functionality
    8. 7.8  Device Hardware Features
      1. 7.8.1  Voltage References
      2. 7.8.2  ADC Multiplexer
      3. 7.8.3  LDOs
        1. 7.8.3.1 Preregulator Control
        2. 7.8.3.2 REG1 and REG2 LDO Controls
      4. 7.8.4  Standalone Versus Host Interface
      5. 7.8.5  Multifunction Pin Controls
      6. 7.8.6  RST_SHUT Pin Operation
      7. 7.8.7  CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
      8. 7.8.8  ALERT Pin Operation
      9. 7.8.9  DDSG and DCHG Pin Operation
      10. 7.8.10 Fuse Drive
      11. 7.8.11 Cell Open Wire
      12. 7.8.12 Low Frequency Oscillator
      13. 7.8.13 High Frequency Oscillator
    9. 7.9  Device Functional Modes
      1. 7.9.1 Overview
      2. 7.9.2 NORMAL Mode
      3. 7.9.3 SLEEP Mode
      4. 7.9.4 DEEPSLEEP Mode
      5. 7.9.5 SHUTDOWN Mode
      6. 7.9.6 CONFIG_UPDATE Mode
    10. 7.10 Serial Communications Interface
      1. 7.10.1 Serial Communications Overview
      2. 7.10.2 I2C Communications
      3. 7.10.3 SPI Communications
        1. 7.10.3.1 SPI Protocol
      4. 7.10.4 HDQ Communications
    11. 7.11 Cell Balancing
      1. 7.11.1 Cell Balancing Overview
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements (Example)
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plot
      4. 8.2.4 Calibration Process
    3. 8.3 Random Cell Connection Support
    4. 8.4 Startup Timing
    5. 8.5 FET Driver Turn-Off
    6. 8.6 Unused Pins
    7. 8.7 Power Supply Requirements
    8. 8.8 Layout
      1. 8.8.1 Layout Guidelines
      2. 8.8.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-43337DD0-CB88-479F-A7DA-DC7DBEEF12A3-low.svg
Table 5-1 BQ76972 TQFP Package (PFB) Pin Functions
PINI/OTYPEDESCRIPTION
NO.NAME
1VC15IIASense voltage input pin for the fifteenth cell from the bottom of the stack, balance current input for the fifteenth cell from the bottom of the stack, and return balance current for the sixteenth cell from the bottom of stack
2VC14IIASense voltage input pin for the fourteenth cell from the bottom of the stack, balance current input for the fourteenth cell from the bottom of the stack, and return balance current for the fifteenth cell from the bottom of the stack
3VC13IIASense voltage input pin for the thirteenth cell from the bottom of the stack, balance current input for the thirteenth cell from the bottom of the stack, and return balance current for the fourteenth cell from the bottom of the stack
4VC12IIASense voltage input pin for the twelfth cell from the bottom of the stack, balance current input for the twelfth cell from the bottom of the stack, and return balance current for the thirteenth cell from the bottom of the stack
5VC11IIASense voltage input pin for the eleventh cell from the bottom of the stack, balance current input for the eleventh cell from the bottom of the stack, and return balance current for the twelfth cell from the bottom of the stack
6VC10IIASense voltage input pin for the tenth cell from the bottom of the stack, balance current input for the tenth cell from the bottom of the stack, and return balance current for the eleventh cell from the bottom of the stack
7VC9IIASense voltage input pin for the ninth cell from the bottom of the stack, balance current input for the ninth cell from the bottom of the stack, and return balance current for the tenth cell from the bottom of the stack
8VC8IIASense voltage input pin for the eighth cell from the bottom of the stack, balance current input for the eighth cell from the bottom of the stack, and return balance current for the ninth cell from the bottom of the stack
9VC7IIASense voltage input pin for the seventh cell from the bottom of the stack, balance current input for the seventh cell from the bottom of the stack, and return balance current for the eighth cell from the bottom of the stack
10VC6IIASense voltage input pin for the sixth cell from the bottom of the stack, balance current input for the sixth cell from the bottom of the stack, and return balance current for the seventh cell from the bottom of the stack
11VC5IIASense voltage input pin for the fifth cell from the bottom of the stack, balance current input for the fifth cell from the bottom of the stack, and return balance current for the sixth cell from the bottom of the stack
12VC4IIASense voltage input pin for the fourth cell from the bottom of the stack, balance current input for the fourth cell from the bottom of the stack, and return balance current for the fifth cell from the bottom of the stack
13VC3IIASense voltage input pin for the third cell from the bottom of the stack, balance current input for the third cell from the bottom of the stack, and return balance current for the fourth cell from the bottom of the stack
14VC2IIASense voltage input pin for the second cell from the bottom of the stack, balance current input for the second cell from the bottom of the stack, and return balance current for the third cell from the bottom of the stack
15VC1IIASense voltage input pin for the first cell from the bottom of the stack, balance current input for the first cell from the bottom of the stack, and return balance current for the second cell from the bottom of the stack
16VC0IIASense voltage input pin for the negative terminal of the first cell from the bottom of the stack, and return balance current for the first cell from the bottom of the stack
17VSS—PDevice ground
18SRPIIAAnalog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN, where SRP is the top of the sense resistor. A charging current generates a positive voltage at SRP relative to SRN.
19NC——This pin is not connected to silicon.
20SRNIIAAnalog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN, where SRN is the bottom of the sense resistor. A charging current generates a positive voltage at SRP relative to SRN.
21TS1I/OOD, I/OAThermistor input, or general purpose ADC input
22TS2I/OOD, I/OAThermistor input and functions as wakeup from SHUTDOWN, or general purpose ADC input
23TS3I/OOD, I/OAThermistor input, or general purpose ADC input
24REG18OPInternal 1.8-V LDO output (only for internal use)
25ALERTI/OI/OD, I/OAMultifunction pin, can be ALERT output, or HDQ I/O, or thermistor input, or general purpose ADC input, or general purpose digital output
26SCLI/OI/ODMultifunction pin, can be SCL or SPI_SCLK
27SDAI/OI/ODMultifunction pin, can be SDA or SPI_MISO
28HDQI/OI/OD, I/OAMultifunction pin, can be HDQ I/O, SPI_MOSI, thermistor input, general purpose ADC input, or general purpose digital output
29CFETOFFI/OI/OD, I/OAMultifunction pin, can be CFETOFF, SPI_CS, thermistor input, general purpose ADC input, or general purpose digital output
30DFETOFFI/OI/OD, I/OAMultifunction pin, can be DFETOFF, BOTHOFF, thermistor input, general purpose ADC input, or general purpose digital output
31DCHGI/OOD, I/OAMultifunction pin, can be DCHG, thermistor input, general purpose ADC input, or general purpose digital output
32DDSGI/OOD, I/OAMultifunction pin, can be DDSG, thermistor input, general purpose ADC input, or general purpose digital output
33RST_SHUTIIDDigital input pin for reset or shutdown
34REG2OPSecond LDO (REG2) output, which can be programmed for 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V.
35REG1OPFirst LDO (REG1) output, which can be programmed for 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V.
36REGINIIAInput pin for REG1 and REG2 LDOs
37BREGOOABase control signal for external preregulator transistor
38FUSEI/OI/OAFuse sense and drive
39PDSGOOAPredischarge PFET control
40PCHGOOAPrecharge PFET control
41LDI/OI/OALoad detect pin
42PACKIIAPack sense input pin
43DSGOOANMOS Discharge FET drive output pin
44NC——This pin is not connected to silicon.
45CHGOOANMOS Charge FET drive output pin
46CP1I/OI/OACharge pump capacitor
47BATIPPrimary power supply input pin
48VC16IIASense voltage input pin for the sixteenth cell from the bottom of the stack, balance current input for the sixteenth cell from the bottom of the stack, and top-of-stack measurement point