SLUSAM3A May   2011  – December 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: AC SPI Data Interface
    7. 6.7 Vertical Communications Bus
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog-to-Digital Conversion (ADC)
        1. 7.3.1.1  General Features
        2. 7.3.1.2  3-to-6 Series Cell Configuration
        3. 7.3.1.3  Cell Voltage Measurements
        4. 7.3.1.4  GPAI or VBAT Measurements
          1. 7.3.1.4.1 Converting GPAI Result to Voltage
          2. 7.3.1.4.2 Converting VBAT Result to Voltage
        5. 7.3.1.5  Temperature Measurement
          1. 7.3.1.5.1 External Temperature Sensor Support (TS1+, TS1-, TS2+, and TS2-)
          2. 7.3.1.5.2 Converting TSn Result to Voltage (Ratio)
        6. 7.3.1.6  ADC Band-Gap Voltage Reference
        7. 7.3.1.7  Conversion Control
          1. 7.3.1.7.1 Convert Start
            1. 7.3.1.7.1.1 Hardware Start
            2. 7.3.1.7.1.2 Firmware Start
          2. 7.3.1.7.2 Data Ready
          3. 7.3.1.7.3 ADC Channel Selection
          4. 7.3.1.7.4 Conversion Time Control
          5. 7.3.1.7.5 Automatic Versus Manual Control
        8. 7.3.1.8  Secondary Protection
          1. 7.3.1.8.1 Protector Functionality
            1. 7.3.1.8.1.1 Using the Protector Functions With 3-5 Cells
        9. 7.3.1.9  Cell Overvoltage Fault Detection (COV)
        10. 7.3.1.10 Cell Undervoltage Fault Detection (CUV)
        11. 7.3.1.11 Overtemperature Detection
          1. 7.3.1.11.1 Ratiometric Sensing
          2. 7.3.1.11.2 Thermistor Power
          3. 7.3.1.11.3 Thermistor Input Conditioning
        12. 7.3.1.12 Fault and Alert Behavior
          1. 7.3.1.12.1 Fault Recovery Procedure
        13. 7.3.1.13 Secondary Protector Built-In Self-Test Features
      2. 7.3.2 Cell Balancing
        1. 7.3.2.1 Cell Balance Control Safety Timer
      3. 7.3.3 Other Features and Functions
        1. 7.3.3.1 Internal Voltage Regulators
          1. 7.3.3.1.1 Internal 5-V Analog Supply
          2. 7.3.3.1.2 Internal 5-V Digital Supply
          3. 7.3.3.1.3 Low-Dropout Regulator (REG50)
          4. 7.3.3.1.4 Auxiliary Power Output (AUX)
        2. 7.3.3.2 Undervoltage Lockout and Power-On Reset
          1. 7.3.3.2.1 UVLO
          2. 7.3.3.2.2 Power-On Reset (POR)
          3. 7.3.3.2.3 Reset Command
        3. 7.3.3.3 Thermal Shutdown (TSD)
        4. 7.3.3.4 GPIO
      4. 7.3.4 Communications
        1. 7.3.4.1 SPI Communications - Device to Host
        2. 7.3.4.2 Device-to-Device Vertical Bus (VBUS) Interface
        3. 7.3.4.3 Packet Formats
          1. 7.3.4.3.1 Data Read Packet
          2. 7.3.4.3.2 Data Write Packet
          3. 7.3.4.3.3 Broadcast Writes
          4. 7.3.4.3.4 Communications Packet Structure
          5. 7.3.4.3.5 CRC Algorithm
          6. 7.3.4.3.6 Data Packet Usage Examples
        4. 7.3.4.4 Device Addressing
    4. 7.4 Device Functional Modes
      1. 7.4.1 SLEEP Functionality
        1. 7.4.1.1 SLEEP State Entry (Bit Set)
        2. 7.4.1.2 SLEEP State Exit (Bit Reset)
    5. 7.5 Programming
      1. 7.5.1 Programming the EPROM Configuration Registers
    6. 7.6 Register Maps
      1. 7.6.1 I/O Register Details
      2. 7.6.2 Register Types
        1. 7.6.2.1 Read-Only (Group 1)
        2. 7.6.2.2 Read / Write (Group 2)
        3. 7.6.2.3 Read / Write, Initialized From EPROM (Group3)
        4. 7.6.2.4 Error Checking and Correcting (ECC) EPROM
      3. 7.6.3 Register Details
        1. 7.6.3.1  DEVICE_STATUS Register (0x00)
        2. 7.6.3.2  GPAI (0x01, 0x02) Register
        3. 7.6.3.3  VCELLn Register (0x03…0x0e)
        4. 7.6.3.4  TEMPERATURE1 Register (0x0f, 0x10)
        5. 7.6.3.5  TEMPERATURE2 Register (0x11, 0x12)
        6. 7.6.3.6  ALERT_STATUS Register (0x20)
        7. 7.6.3.7  FAULT_STATUS Register (0x21)
        8. 7.6.3.8  COV_FAULT Register (0x22)
        9. 7.6.3.9  CUV_FAULT Register (0x23)
        10. 7.6.3.10 PARITY_H Register (0x24) [PRESULT_A (R/O)]
        11. 7.6.3.11 PARITY_H Register (0x25) [PRESULT_B (R/O)]
        12. 7.6.3.12 ADC_CONTROL Register (0x30)
        13. 7.6.3.13 IO_CONTROL Register (0x31)
        14. 7.6.3.14 CB_CTRL Register (0x32)
        15. 7.6.3.15 CB_TIME Register (0x33)
        16. 7.6.3.16 ADC_CONVERT Register (0x34)
        17. 7.6.3.17 SHDW_CTRL Register (0x3a)
        18. 7.6.3.18 ADDRESS_CONTROL Register (0x3b)
        19. 7.6.3.19 RESET Register (0x3c)
        20. 7.6.3.20 TEST_SELECT Register (0x3d)
        21. 7.6.3.21 E_EN Register (0x3f)
        22. 7.6.3.22 FUNCTION_CONFIG Register (0x40)
        23. 7.6.3.23 IO_CONFIG Register (0x41)
        24. 7.6.3.24 CONFIG_COV Register (0x42)
        25. 7.6.3.25 CONFIG_COVT Register (0x43)
        26. 7.6.3.26 CONFIG_UV Register (0x44)
        27. 7.6.3.27 CONFIG_CUVT Register (0x45)
        28. 7.6.3.28 CONFIG_OT Register (0x46)
        29. 7.6.3.29 CONFIG_OTT Register (0x47)
        30. 7.6.3.30 USERx Register (0x48-0x4b) (USER1-4)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Anti-Aliasing Filter
      2. 8.1.2 Host SPI Interface Pin States
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Decoupling
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The bq76PL536A-Q1 is a series cell Lithium-Ion battery monitor and secondary protector for Electric Vehicles (EV), Hybrid Electric Vehicles (HEV), Uninterruptible Power Systems (UPS), E-Bike/Scooter, Large-Format Battery Systems, and so forth.

To allow for optimal performance in the end application, special consideration must be taken to ensure minimization of measurement error through proper printed circuit board (PCB) layout.

8.1.1 Anti-Aliasing Filter

An anti-aliasing filter is required for each VCn input VC6–VC1, consisting of a 1-kΩ, 1% series resistor and 100-nF capacitor. Good-quality components should be used. A 1% resistor is recommended, because the resistor creates a small error by forming a voltage divider with the input impedance of the part. The part is factory-trimmed to compensate for the error introduced by the filter.

8.1.2 Host SPI Interface Pin States

The CS_H pin is active-low. The host asserts the pin to a logic zero to initiate communications. The CS pin should remain low until the end of the current packet. When the CS_H pin is asserted, the SPI receiver and interface of the device are reset and resynchronized. This action ensures that a slave device that has lost synchronization during a previous transmission or as the result of noise on the bus does not remain permanently hung. CS_H must be driven false (high) between packets; see Timing Requirements: AC SPI Data Interface, for timing details.

8.2 Typical Application

Full-size reference schematics are available from TI on request.

bq76PL536A-Q1 S001_LUSAB1.gif Figure 56. Schematic (Page 1 of 4)
bq76PL536A-Q1 S002_LUSAB1.gif Figure 57. Schematic (Page 2 of 4)
bq76PL536A-Q1 S003_LUSAB1.gif Figure 58. Schematic (Page 3 of 4)
bq76PL536A-Q1 S004_LUSAB1.gif Figure 59. Schematic (Page 4 of 4)

8.2.1 Design Requirements

For this design example, use the parameters listed in Table 9.

Table 9. Design Parameters

PARAMETER DESCRIPTION EXAMPLE VALUE UNIT
CEMI EMI Capacitor 3300 pF
CFILT Filter Capacitor 0.1 µF
CIN Input Capacitor 0.1 µF
CREGOUT REGOUT Capacitor 2.2 (minimum) µF
CVDDA_1 Internal analog 5-V LDO bypass connection 1 2.2 µF
CVDDA_2 Internal analog 5-V LDO bypass connection 2 0.2 µF
CVDD_D_1 Capacitor for internal digital 5-V LDO bypass connection 1 2.2 µF
CVDD_D_2 Capacitor for internal digital 5-V LDO bypass connection 2 0.2 µF
CVREF VREF Capacitor 10 µF
LEMI EMI Ferrite Resistor 500 Ω
RBAL Balance Resistor 47 Ω
RIN Input Resistor 1 kΩ
RPULL1-RPULL3 Pullup Resistors for digital open-drain I/O 10 kΩ
RPULL4-RPULL5 Pullup Resistors for general-purpose (differential) analog input (GPAI), connect to VSS if unused kΩ

8.2.2 Detailed Design Procedure

Use the following for the procedure for the recommended front-end circuit:

  1. Select the RC filter closest to the cell for filter requirements. Additional poles can be added with a differential capacitor to get very low fc.
  2. ADC is calibrated to use RIN = 1 kΩ and CIN = 0.1 µF.
  3. Select Zener diode for lowest possible reverse leakage.
  4. A balance FET gate-protection diode is required (available internally).
  5. Select the capacitors for LDO Filters according to Table 9.
    • LDO1 and LDO2 require a 2.2-µF ceramic capacitor for stability. These pins are tied together internally. Tie LDO1 to LDOD2 externally.
  6. For pullup supply, the following information applies:
    1. REG50 turns off in SLEEP mode
    2. Use LDOD for pullups in normal use
    3. Use REG50 for programming EEPROM (LDOD will see 7 V)
    4. Connect GPAI+ and GPA– to VSS if unused
  7. Select low impedance and polarized connectors. Numbered or colored connectors are also good options.
  8. Select the input Zener TVS so that it clamps below 5.6 Vdc, with low-leakage current, and must be able to handle transient surge energy
  9. Select capacitors based on temperature and environment with voltages well above the operating voltage
  10. Select balancing MOSFETs according to the following:
    1. Low turn on threshold voltage (must turn on with the lowest cell voltage)
    2. Drain-to-source voltage and gate-to-source voltage
    3. Power dissipation
    4. Current based on selected bleed resistor value
  11. Select the Bleed Resistor according to the following:
    1. Value based on desired current
    2. Wattage to handle the current and temperature rise such as 4.2 V × 47 = 0.089 A ∴ 0.37 W)

8.2.3 Application Curves

bq76PL536A-Q1 firmwareconvadc_on.gif
Figure 60. Firmware Conversion with ADC_ON = 0
bq76PL536A-Q1 hardwareconvadcon0.gif
Figure 62. Hardware Conversion with ADC_ON = 0
bq76PL536A-Q1 zoominhwconv.gif
Figure 64. ZOOM IN Hardware Conversion
bq76PL536A-Q1 firmwareconvadc_on1.gif
Figure 61. Firmware Conversion with ADC_ON = 1
bq76PL536A-Q1 hardwareconvadcon1.gif
Figure 63. Hardware Conversion with ADC_ON = 1