SUPPLY CURRENT |
ICCSLEEP |
Supply current |
No load at REG50, SCLK_N, SDI_N, SDO_N, FAULT_N, CONV_N, DRDY_S, ALERT_N, TSx, AUX, or CBx; CB_CTRL = 0; CBT_CONTROL = 0; CONV_H = 0 (not converting), IO_CTRL[SLEEP] = 1 |
|
12 |
20 |
µA |
ICCPROTECT |
Supply current |
No load at REG50, SCLK_N, SDI_N, SDO_N, FAULT_N, CONV_N, DRDY_S, ALERT_N, TSx, AUX, or CBx; CB_CTRL = 0; CBT_CONTROL = 0; CONV_H = 0 (not converting), IO_CTRL[SLEEP] = 0 |
|
45 |
60 |
µA |
ICCBALANCE |
Supply current |
No load at REG50, SCLK_N, SDI_N, SDO_N, FAULT_N, CONV_N, DRDY_S, ALERT_N, TSx, or AUX; No DC load at CBx; CB_CTRL ≠ 0; CBT_CONTROL ≠ 0; CONV_H = 0 (not converting) , IO_CTRL[SLEEP] = 0 |
|
46 |
60 |
µA |
ICCCONVERT |
Supply current |
No load at REG50, SCLK_N, SDI_N, SDO_N, FAULT_N, CONV_N, DRDY_S, ALERT_N, TSx or CBx; CONV_S = 1 (conversion active) , IO_CTRL[SLEEP] = 0 |
|
10.5 |
15 |
mA |
ICCTSD |
Supply current |
Thermal shutdown activated; ALERT_STATUS[TSD] = 1 |
|
1.6 |
|
mA |
REG50, INTEGRATED 5-V LDO |
VREG50 |
Output voltage |
IREG50OUT ≤ 0.5 mA, C = 2.2 μF to 22 μF |
4.9 |
5 |
5.1 |
V |
ΔVREG50LINE |
Line regulation |
6 V ≤ BAT ≤ 27 V, IREG50OUT = 2 mA |
|
10 |
25 |
mV |
ΔVREG50LOAD |
Load regulation |
0.2 mA ≤ IREG50OUT ≤ 2 mA |
|
|
15 |
mV |
0.2 mA ≤ IREG50OUT ≤ 5 mA |
|
|
25 |
IREG50MAX |
Current limit |
|
12 |
25 |
35 |
mA |
IAUXMAX |
Maximum load |
AUX pin |
|
|
5 |
mA |
RAUX |
AUX output |
I = 1 mA, max. capacitance = VREG50
Capacitor: CVAUX ≤ CVREG50 / 10 |
|
|
50 |
Ω |
LEVEL SHIFT INTERFACE |
INTX1 |
North 1 transmitter current |
SCLK_N, CS_N, SDI_N, CONV_N |
1000 |
1350 |
1800 |
µA |
INTX0 |
North 0 transmitter current |
CS_N, CONV_N |
|
|
1 |
µA |
INTX0A |
North 0 transmitter current |
SCLK_N, SDI_N (BASE device CS_H = 1) |
|
|
1 |
µA |
INTX0B |
North 0 transmitter current |
SCLK_N, SDI_N (BASE device CS_H = 0) |
50 |
75 |
110 |
µA |
ISRX |
South 1 receiver threshold |
SCLK_S, CS_S, SDI_S, CONV_S |
430 |
550 |
680 |
µA |
ISRXH |
South receiver hysteresis |
SCLK_S, CS_S, SDI_S, CONV_S |
50 |
100 |
200 |
µA |
ISTX1 |
South 1 transmitter current |
ALERT_N, FAULT_S, DRDY_S |
800 |
1100 |
1400 |
µA |
ISTX0 |
South 0 transmitter current |
ALERT_S, FAULT_S, DRDY_S |
|
|
1 |
µA |
ISTX0B |
South 0 transmitter current |
SDO_S (BASE device CS_H = 0) |
1 |
4 |
7 |
µA |
INRX |
North 1 receiver threshold |
SDO_N, ALERT_N, FAULT_N, DRDY_N |
420 |
580 |
720 |
µA |
INRXH |
North receiver hysteresis |
SDO_N, ALERT_N, FAULT_N, DRDY_N |
50 |
100 |
200 |
µA |
CIN |
Input capacitance |
|
|
15 |
|
pF |
HOST INTERFACE |
VOH |
Logic-level output voltage, high; SDO_H, FAULT_H, ALERT_H, DRDY |
CL = 20 pF, IOH < 5 mA(1) |
4.5 |
|
VLDOD |
V |
VOL |
Logic-level output voltage, low; SDO_H, FAULT_H, ALERT_H, DRDY |
CL = 20 pF, IOL < 5 mA(1) |
VSS |
|
0.5 |
V |
VIH |
Logic-level input voltage, high; SCLK_H, SDI_H, CS_H, CONV |
|
2 |
|
5.2 |
V |
VIL |
Logic-level input voltage, low; SCLK_H, SDI_H, CS_H, CONV |
|
VSS |
|
0.8 |
V |
CIN |
Input capacitance SCLK_H, SDI_H, CS_H, CONV |
|
|
5 |
|
pF |
ILKG |
Input leakage current SCLK_H, SDI_H, CS_H, CONV |
|
|
|
1 |
µA |
GENERAL PURPOSE INPUT/OUTPUT (GPIO) |
VIH |
Logic-level input voltage, high |
Vin ≤ VREG50 |
2 |
|
|
V |
VIL |
Logic-level input voltage, low |
|
|
|
0.8 |
V |
VOH |
Output high-voltage pullup voltage |
Supplied by external approximately100-kΩ resistor |
|
|
VREG50 |
V |
VOL |
Logic-level output voltage, low |
IOL = 1 mA |
0.3 |
|
|
V |
CIN |
Input capacitance(1) |
|
|
5 |
|
pF |
ILKG |
Input leakage current |
|
|
|
1 |
µA |
CELL BALANCING CONTROL OUTPUT (CBx) |
CBz |
Output impedance |
1 V < VCELL < 5 V |
80 |
100 |
120 |
kΩ |
VRANGE |
Output V |
|
VCn-1 |
|
VCn |
V |
ADC COMMON SPECIFICATIONS |
tCONV_START |
CONV high to conversion start(2) (3) |
ADC_CONTROL[ADC_ON] = 1 |
5.4 |
6 |
6.6 |
µs |
ADC_CONTROL[ADC_ON] = 0 |
|
500 |
|
µs |
tCONV |
Conversion time per selected channel(4) |
ADC_CONTROL[ADC_ON] = 1 |
5.4 |
6 |
6.6 |
µs |
ILKG |
Input leakage current |
Not converting |
|
<10 |
100 |
nA |
VCn (CELL) INPUTS |
VIN |
Input voltage range(5) |
VCn – VCn–1, where n = 1 to 6 |
0 |
|
6 |
V |
VRES |
Voltage resolution(6) |
14 bits |
|
~378 |
|
µV |
VACC |
Voltage accuracy, total error, VIN = VCn to VCn–1 |
–10°C ≤ TA ≤ 50°C, 1.2 V < VIN < 4.5 V |
–5 |
±1 |
5 |
mV |
–40°C ≤ TA ≤ 85°C, 1.2 V < VIN < 4.5 V |
–8 |
|
8 |
RIN |
Effective input resistance |
Converting |
|
2 |
|
MΩ |
CIN |
Input capacitance |
Converting |
|
1 |
|
pF |
EN |
Noise |
VIN = 3 V |
|
|
250 |
µVRMS |
VBAT (VBRICK) MEASUREMENT |
VIN |
Input voltage range(5), BATn to VSS |
FUNCTION_CONFIG = 0101xx00b |
0 |
|
30 |
V |
VRES |
Voltage resolution(6) |
14 bits |
|
~1.831 |
|
mV |
VACC |
Voltage accuracy |
Total error |
–80 |
–30 |
20 |
mV |
CIN |
Input capacitance |
Converting |
|
1 |
|
pF |
RIN |
Effective input resistance |
Converting |
|
50 |
|
kΩ |
EN |
Noise |
|
|
|
1.5 |
mVRMS |
GPAI MEASUREMENT |
VIN |
Input voltage range,(5) GPAI+ to GPAI– |
|
0 |
|
2.5 |
V |
VRES |
Voltage resolution(6) |
14 bits |
|
~153 |
|
µV |
VACC |
Voltage accuracy, VIN = GPAI+ – GPAI– |
0.25 V ≤ VIN ≤ 2.5 V |
–7 |
|
7 |
mV |
VIN = 1.25 V, TA = 25°C |
|
±2 |
|
CIN |
Input capacitance |
Converting |
|
40 |
|
pF |
RIN |
Effective input resistance |
Converting |
|
50 |
|
KΩ |
EN |
Noise |
|
|
|
150 |
µVRMS |
TSn MEASUREMENT |
VRES |
Voltage resolution,(6) |
14 bits, REG50 = 5 V, (Resolution ≈ VREG50 / 215) |
|
~153 |
|
µV |
VACC |
Ratio accuracy, % of input(6) |
0.25 V ≤ VIN ≤ 2.4 V |
–0.7% |
±0.2% |
0.7% |
|
CIN |
Input capacitance |
Converting |
|
40 |
|
pF |
RIN |
Effective input resistance |
Converting |
|
50 |
|
kΩ |
EN |
Noise |
|
|
|
150 |
µVRMS |
THERMAL SHUTDOWN |
TSD |
Shutdown threshold |
VBAT = 20 V |
125 |
142 |
156 |
°C |
THYS |
Recovery hysteresis |
|
|
8 |
25 |
°C |
UNDERVOLTAGE LOCKOUT (UVLO) and POWER-ON RESET (POR) |
VUVLO |
Negative-going threshold |
|
5 |
|
5.6 |
V |
VUVLO_HSY |
Hysteresis |
|
250 |
375 |
500 |
mV |
UVLODELAY |
Delay to locked-out condition |
V ≤ VUVLO MIN |
|
15 |
|
µs |
VPOR |
Negative-going threshold |
|
4 |
|
5 |
V |
VPOR_HSY |
Hysteresis |
|
250 |
500 |
750 |
mV |
PORDELAY |
Delay to disabled condition |
V ≤ VPOR MIN |
|
15 |
|
µs |
tRST |
Reset delay time |
V ≥ VPOR + VPOR_HSY |
40 |
56 |
70 |
ms |
VDELTA_RISE |
Voltage delta between trip points |
VUVLO – VPOR (VBAT rising) |
0.3 |
0.4 |
0.7 |
V |
VDELTA_FALL |
Voltage delta between trip points |
VUVLO – VPOR (VBAT falling) |
0.4 |
0.52 |
0.7 |
V |
BATTERY PROTECTION THRESHOLDS |
VOVR |
OV detection threshold range(7) |
|
2 |
|
5 |
V |
ΔVOVS |
OV detection threshold program step |
|
|
50 |
|
mV |
VOVH |
OV detection hysteresis |
|
|
50 |
|
mV |
VOVA1 |
OV detection threshold accuracy |
3.3 ≤ VOV_SET ≤ 4.5 |
–50 |
0 |
50 |
mV |
VOVA2 |
OV detection threshold accuracy |
VOV_SET < 3.3 or VOV_SET > 4.5 |
–70 |
0 |
70 |
mV |
VUVR |
UV detection threshold range(7) |
|
700 |
|
3300 |
mV |
ΔVUVS |
UV detection threshold program step |
|
|
100 |
|
mV |
VUVH |
UV detection hysteresis |
|
|
100 |
|
mV |
VUVA |
UV detection threshold accuracy |
|
–100 |
0 |
100 |
mV |
VOTR |
OT detection threshold range(8) |
VREG50 = 5 V |
1 |
|
2 |
V |
ΔVOTS |
OT detection threshold program step(8) |
|
|
See (9) |
|
V |
VOTA |
OT detection threshold accuracy(8) |
T = 40°C to 90°C |
|
0.04 |
0.05 |
V |
ΔVOTH |
OT reset hysteresis |
T = 40°C to 90°C |
8% |
12% |
15% |
|
BATTERY PROTECTION DELAY TIMES |
tOV |
OV detection delay-time range |
|
0 |
|
3200 |
ms |
ΔtOV |
OV detection delay-time step |
COVT [µs] = 0 |
|
100 |
|
µs |
COVT [ms] = 1 |
|
100 |
|
ms |
tUV |
UV detection delay-time range |
|
0 |
|
3200 |
ms |
ΔtUV |
UV detection delay-time step |
CUVT[7] (µs) = 0 |
|
100 |
|
µs |
CUVT[7] (ms) = 1 |
|
100 |
|
ms |
tOT |
OT detection delay-time range |
|
0 |
|
2550 |
ms |
ΔtOT |
OT detection delay-time step |
|
|
10 |
|
ms |
tacr |
OV, UV, and OT detection delay-time accuracy(10) |
CUVT, (COVT) ≥ 500 µs |
–12% |
0% |
10% |
|
t(DETECT) |
Protection comparator detection time |
VOT or VOV or VUV threshold exceeded by 10 mV |
|
|
100 |
µs |
OTP EPROM PROGRAMMING CHARACTERISTICS |
VPROG |
Programming voltage |
VBAT ≥ 20 V |
6.75 |
7 |
7.25 |
V |
tPROG |
Programming time |
VBAT ≥ 20 V |
(11) |
|
50 |
ms |
IPROG |
Programming current |
VBAT ≥ 20 V |
|
10 |
20 |
mA |