This value depends on the cell chemistry and the load requirements of the system. For example, to support a minimum battery voltage of 12 V using Li-CO2 type cells with a cell minimum voltage of 3 V, at least 4-series cells are required.
For the correct cell connections, see Section 7.4.3.
Protection FET selection and configuration
The BQ77307 device is designed for use with low-side NFET protection
The configuration should be selected for series versus parallel FETs, which may lead to different FET selection for charge versus discharge direction.
These FETs should be rated for the maximum:
Voltage, which should be approximately 5 V (DC) to 10 V (peak) per series cell.
Current, which should be calculated based on both the maximum DC current and the maximum transient current with some margin.
Power Dissipation, which can be a factor of the RDS(ON) rating of the FET, the FET package, and the PCB design.
Sense resistor selection
The resistance value should be selected to maximize the input range of the SCD, OCD, and OCC protections but not exceed the absolute maximum ratings, and avoid excessive heat generation within the resistor.
Using the normal maximum charge or discharge current, the sense resistor = 200 mV / 40.0 A = 5 mΩ maximum.
Considering a short circuit discharge current of 80 A, the recommended maximum SRP, SRN voltage of ≈0.75 V, and the maximum SCD threshold of 500 mV, the sense resistor should be below 500 mV / 80 A= 6.25 mΩ maximum.
Further tolerance analysis (value tolerance, temperature variation, and so on) and PCB design margin should also be considered, so a sense resistor of 1 mΩ is suitable with a 50-ppm temperature coefficient and power rating of 1 W.
The REGOUT is selected to provide the supply for an external host processor and the pullup supply for the I2C bus and ALERT pin, with output voltage selected for 3.3 V.
A 1 μF or larger capacitor should be placed at the REGOUT pin.
The REGOUT draws its input current from the REGSRC pin. This pin is connected to PACK+ through a series diode and 10 Ω resistor, with a 1-μF capacitor to VSS placed at the REGSRC pin.