The low-side CHG and DSG FET drivers operate differently when they are triggered to turn off their respective FET. The DSG driver includes an internal switch that drives the DSG pin toward the VSS pin level when the driver is disabled. The driver is specified with a maximum fall time into a 20-nF capacitive load, with 100-Ω series resistance between the DSG pin and the DSG gate. If the driver is used with a larger capacitive load, the fall time generally increases. The system designer can optimize the series resistance value based on the board components and DSG FET(s) used.

The external series gate resistor between the DSG pin and the DSG FET gate is used to adjust the speed of the turn-off transient. A low resistance (such as 100 Ω) provides a fast turn-off during a short circuit event, but this may result in an overly large inductive spike at the top of stack when the FET is disabled. A larger resistor value (such as 1 kΩ or 4.7 kΩ) reduces this speed and the corresponding inductive spike level.

The CHG FET driver discharges the CHG pin toward the VSS pin level, but it includes an additional series PFET to support voltages below VSS. This is generally needed when a pack is heavily discharged, for example, if cells in a 7-S pack are at 2.5 V per cell, then PACK+ = 17.5 V relative to device VSS. Then if a charger is attached while the CHG FET is disabled and applies a full charge voltage across PACK+ relative to PACK-, such as 4.3 V per cell, or 30.1 V for the 7-S pack, this results in PACK- dropping to approximately –12.6 V relative to VSS. To keep the CHG FET disabled, its gate voltage must drop to near this –12 V level.

To support this type of case, the CHG FET driver in BQ77307 is designed to withstand voltages as low as –25 V (recommended) relative to the VSS pin voltage by including a series PFET at the pin, with its gate connected to VSS. When the CHG driver is disabled, the driver pulls the pin voltage downward. As the pin voltage nears VSS, the PFET is disabled, so the pin becomes high impedance. At this point, the external gate-source resistor on the CHG FET pulls the pin voltage lower to the PACK– level, keeping the CHG FET disabled.

Oscilloscope captures of the DSG driver turn-off are shown below, with the DSG pin driving the gate of a CSD18532Q5B NFET, which has a typical C_iss of 3900 pF. Figure 8-10 shows the signals when using a 1.35-kΩ series gate resistor between the DSG pin and the FET gate, and a 2A load connected between PACK+ and PACK–.

Figure 8-5 Moderate Speed DSG FET Turn-Off, Using a 1.35-kΩ Series Gate Resistor, and a 2A Load Between PACK+ and PACK–

A slower turn-off case is shown in Figure 8-6, using a 4.7-kΩ series gate resistor, and a 2A load between PACK+ and PACK–.

Figure 8-6 A Slower Turn-Off Case Using a 4.5-kΩ Series Gate Resistor

A fast turn-off case is shown in Figure 8-7, in which a 100-Ω series gate resistor is used between the DSG pin and the FET gate.

Figure 8-7 A Fast Turn-Off Case with a 100-Ω Series Gate Resistor