JAJSCB2K April   2020  – July 2020 BQ77904 , BQ77905

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Device Functionality Summary
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Protection Summary
      2. 8.3.2  Fault Operation
        1. 8.3.2.1  Operation in OV
        2. 8.3.2.2  Operation in UV
        3. 8.3.2.3  Operation in OW
        4. 8.3.2.4  Operation in OCD1
        5. 8.3.2.5  Operation in OCD2
        6. 8.3.2.6  Operation in SCD
        7. 8.3.2.7  Overcurrent Recovery Timer
        8. 8.3.2.8  Load Removal Detection
        9. 8.3.2.9  Load Removal Detection in UV
        10. 8.3.2.10 Operation in OTC
        11. 8.3.2.11 Operation in OTD
        12. 8.3.2.12 Operation in UTC
        13. 8.3.2.13 Operation in UTD
      3. 8.3.3  Protection Response and Recovery Summary
      4. 8.3.4  Configuration CRC Check and Comparator Built-In-Self-Test
      5. 8.3.5  Fault Detection Method
        1. 8.3.5.1 Filtered Fault Detection
      6. 8.3.6  State Comparator
      7. 8.3.7  DSG FET Driver Operation
      8. 8.3.8  CHG FET Driver Operation
      9. 8.3.9  External Override of CHG and DSG Drivers
      10. 8.3.10 Configuring 3-S, 4-S, or 5-S Mode
      11. 8.3.11 Stacking Implementations
      12. 8.3.12 Zero-Volt Battery Charging Inhibition
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
        1. 8.4.1.1 Power-On Reset (POR)
        2. 8.4.1.2 FAULT Mode
        3. 8.4.1.3 SHUTDOWN Mode
        4. 8.4.1.4 Customer Fast Production Test Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Recommended System Implementation
        1. 9.1.1.1 CHG and DSG FET Rise and Fall Time
        2. 9.1.1.2 Protecting CHG and LD
        3. 9.1.1.3 Protecting CHG FET
        4. 9.1.1.4 Using Load Detect for UV Fault Recovery
        5. 9.1.1.5 Temperature Protection
        6. 9.1.1.6 Adding Filter to Sense Resistor
        7. 9.1.1.7 Using a State Comparator in an Application
          1. 9.1.1.7.1 Examples
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Design Example
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.10 Configuring 3-S, 4-S, or 5-S Mode

The BQ77904 supports 3-S and 4-S packs, while the BQ77905 supports 3-S, 4-S, and 5-S packs. To avoid accidentally detecting a UV fault on unused (shorted) cell inputs, the device must be configured for the specific cell count of the pack. This is set with the configuration pin, CCFG, which is mapped as in Table 8-5. The device periodically checks the CCFG status and takes tCCFG_DEG time to detect the pin status.

Table 8-5 CCFG Configurations
CCFGCONFIGURATIONCONNECT TO
< VCCFGL for tCCFG_DEG3 cellsAVSS
Within VCCFGM for tCCFG_DEG4 cellsAVDD
> VCCFGH for tCCFG_DEG5 cellsFloating

The CCFG pin should be tied to the recommended net from Table 8-5. The device compares the CCFG input voltage to the AVDD voltage and should never be set above the AVDD voltage. When the device configuration is for 5 S, leave the CCFG pin floating. The internal pin bias is approximately 30% of the AVDD voltage for the 5-S configuration. Note that the BQ77904 should not be configured in 5-S mode, as this results in a permanent UV fault.