JAJSCB2K April   2020  – July 2020 BQ77904 , BQ77905

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Device Functionality Summary
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Protection Summary
      2. 8.3.2  Fault Operation
        1. 8.3.2.1  Operation in OV
        2. 8.3.2.2  Operation in UV
        3. 8.3.2.3  Operation in OW
        4. 8.3.2.4  Operation in OCD1
        5. 8.3.2.5  Operation in OCD2
        6. 8.3.2.6  Operation in SCD
        7. 8.3.2.7  Overcurrent Recovery Timer
        8. 8.3.2.8  Load Removal Detection
        9. 8.3.2.9  Load Removal Detection in UV
        10. 8.3.2.10 Operation in OTC
        11. 8.3.2.11 Operation in OTD
        12. 8.3.2.12 Operation in UTC
        13. 8.3.2.13 Operation in UTD
      3. 8.3.3  Protection Response and Recovery Summary
      4. 8.3.4  Configuration CRC Check and Comparator Built-In-Self-Test
      5. 8.3.5  Fault Detection Method
        1. 8.3.5.1 Filtered Fault Detection
      6. 8.3.6  State Comparator
      7. 8.3.7  DSG FET Driver Operation
      8. 8.3.8  CHG FET Driver Operation
      9. 8.3.9  External Override of CHG and DSG Drivers
      10. 8.3.10 Configuring 3-S, 4-S, or 5-S Mode
      11. 8.3.11 Stacking Implementations
      12. 8.3.12 Zero-Volt Battery Charging Inhibition
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
        1. 8.4.1.1 Power-On Reset (POR)
        2. 8.4.1.2 FAULT Mode
        3. 8.4.1.3 SHUTDOWN Mode
        4. 8.4.1.4 Customer Fast Production Test Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Recommended System Implementation
        1. 9.1.1.1 CHG and DSG FET Rise and Fall Time
        2. 9.1.1.2 Protecting CHG and LD
        3. 9.1.1.3 Protecting CHG FET
        4. 9.1.1.4 Using Load Detect for UV Fault Recovery
        5. 9.1.1.5 Temperature Protection
        6. 9.1.1.6 Adding Filter to Sense Resistor
        7. 9.1.1.7 Using a State Comparator in an Application
          1. 9.1.1.7.1 Examples
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Design Example
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1.1 Device Functionality Summary

In this and subsequent sections, a number of abbreviations are used to identify specific fault conditions. The fault descriptor abbreviations and their meanings are defined in Table 8-1.

Table 8-1 Device Functionality Summary
FAULT DESCRIPTORFAULT DETECTION THRESHOLD and DELAY OPTIONSFAULT RECOVERY METHOD and SETTING OPTIONS
OVOvervoltage3 V to 4.575 V (25-mV step)0.5, 1, 2, 4.5 sHysteresis0, 100, 200, 400 mV
UVUndervoltage1.2 V to 3 V
(100-mV step for < 2.5 V,
50-mV step for ≥ 2.5 V)		1, 2, 4.5, 9 sHysteresis OR
Hysteresis + Load Removal		200, 400 mV
OWOpen wire (cell to pcb disconnection)0 (disabled), 100, 200, or 400 nA4.5 sRestore bad VCx to pcb connectionVCx > VOW
OTD(1)Overtemperature during discharge65°C or 70°C4.5 sHysteresis10°C
OTC(1)Overtemperature during charge45°C or 50°C4.5 sHysteresis10°C
UTD(1)Undertemperature during discharge–20°C or –10°C4.5 sHysteresis10°C
UTC (1)Undertemperature during charge–5°C or 0°C4.5sHysteresis10°C
OCD1Overcurrent1 during discharge10 mV to 85 mV (5-mV step)10, 20, 45, 90, 180, 350, 700, 1420 msDelay OR
Delay + Load Removal OR
Load Removal		1 s or 9 s
OCD2Overcurrent1 during discharge20 mV to 170 mV (10-mV step)5, 10, 20, 45, 90, 180, 350, 700 ms
SCDShort circuit discharge40 mV to 340 mV (20-mV step)360 µs
CTRCCHG signal override controlDisable via external control or via CHGU signal from the upper device in the stack configuration.tCTRDEG_ONEnable via external control or via CHGU signal from the upper device in the stack configuration.tCTRDEG_OFF
CTRDDSG signal override controlDisable via external control or via DSG signal from the upper device in the stack configuration.tCTRDEG_ONEnable via external control or via DSG signal from the upper device in the stack configuration.tCTRDEG_OFF
(1) These thresholds are target based on temperature, but they are dependent on external components that could vary based on customer selection. The circuit is based on a 103AT NTC thermistor connected to TS and VSS, and a 10-kΩ resistor connected to VTB and TS. Actual thresholds must be determined in mV. Refers to the overtemperature and undertemperature mV threshold in the Electrical Characteristics table.