JAJSEZ9L march   2018  – august 2023 BQ77915

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 概要 (続き)
  7. 6 Device Comparison Table
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Device Functionality Summary
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Protection Summary
      2. 9.3.2  Fault Operation
        1. 9.3.2.1  Operation in OV
        2. 9.3.2.2  Operation in UV
        3. 9.3.2.3  Operation in OW
        4. 9.3.2.4  Operation in OCD1
        5. 9.3.2.5  Operation in OCD2
        6. 9.3.2.6  Programming the OCD1/2 Delay Using the OCDP Pin
        7. 9.3.2.7  Operation in SCD
        8. 9.3.2.8  Operation in OCC
        9. 9.3.2.9  Overcurrent Recovery Timer
        10. 9.3.2.10 Load Detection and Load Removal Detection
        11. 9.3.2.11 Operation in OTC
        12. 9.3.2.12 Operation in OTD
        13. 9.3.2.13 Operation in UTC
        14. 9.3.2.14 Operation in UTD
      3. 9.3.3  Protection Response and Recovery Summary
      4. 9.3.4  Cell Balancing
      5. 9.3.5  HIBERNATE Mode Operation
      6. 9.3.6  Configuration CRC Check and Comparator Built-In-Self-Test
      7. 9.3.7  Fault Detection Method
        1. 9.3.7.1 Filtered Fault Detection
      8. 9.3.8  State Comparator
      9. 9.3.9  DSG FET Driver Operation
      10. 9.3.10 CHG FET Driver Operation
      11. 9.3.11 External Override of CHG and DSG Drivers
      12. 9.3.12 Configuring 3-Series, 4-Series, or 5-Series Modes
      13. 9.3.13 Stacking Implementations
      14. 9.3.14 Zero-Volt Battery Charging Inhibition
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power Modes
        1. 9.4.1.1 Power On Reset (POR)
        2. 9.4.1.2 NORMAL Mode
        3. 9.4.1.3 FAULT Mode
        4. 9.4.1.4 HIBERNATE Mode
        5. 9.4.1.5 SHUTDOWN Mode
        6. 9.4.1.6 Customer Fast Production Test Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Recommended System Implementation
        1. 10.1.1.1 CHG and DSG FET Rise and Fall Time
        2. 10.1.1.2 Protecting CHG and LD
        3. 10.1.1.3 Protecting the CHG FET
        4. 10.1.1.4 Using Load Detect for UV Fault Recovery
        5. 10.1.1.5 Temperature Protection
        6. 10.1.1.6 Adding RC Filters to the Sense Resistor
        7. 10.1.1.7 Using the State Comparator in an Application
          1. 10.1.1.7.1 Examples
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Design Example
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 サード・パーティ製品に関する免責事項
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 用語集
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.1.1 Device Functionality Summary

Table 9-1 Device Functionality Summary
FAULT DESCRIPTORFAULT DETECTION THRESHOLD and DELAY OPTIONSFAULT RECOVERY METHOD and SETTING OPTIONS
OVOvervoltage3 V to 4.575 V (25-mV step)0.5, 1, 2, 4.5 sHysteresis0, 100, 200, 400 mV
UVUndervoltage1.2 V to 3 V
(100-mV step for < 2.5 V,
50-mV step for ≥ 2.5 V)		1, 2, 4.5, 9 sLoad removal + hysteresis0, 200, 400, 800 mV
OWOpen wire (cell to pcb disconnection)0 (disabled), 100 nA, 200 nA, 400 nA4.5 sRestore bad VCx to PCB connectionVCx > VOW
OTD(1)Overtemperature during discharge65°C or 70°C4.5 sHysteresis or load removal + hysteresis10°C
OTC(1)Overtemperature during charge45°C or 50°C4.5 sHysteresis10°C
UTD(1)Undertemperature during discharge–20°C or –10°C4.5 sHysteresis10°C
UTC(1)Undertemperature during charge–5°C or 0°C4.5 sHysteresis10°C
OCCOvercurrent during charge5 mV to 80 mV (5-mV step)10 msTimer auto-release and load detection, timer auto-release only, load detection only250 ms or 500 ms
OCD1Overcurrent1 during discharge–10 mV to –85 mV (5-mV step)10, 20, 45, 90, 180, 350, 700, 1420 msTimer auto-release and load removal, timer auto-release only, load removal only
OCD2Overcurrent1 during discharge–20 mV to –170 mV (10-mV step)5, 10, 20, 45, 90, 180, 350, 700 ms
SCDShort circuit discharge–40 mV to –340 mV (20-mV step)400, 960 µs
CTRCCHG signal override controlDisable through external control or through CHG signal from the upper device in stack configurationtCTRDEG_ONEnable through external control or through the CHG signal from the upper device in stack configurationtCTRDEG_OFF
CTRDDSG signal override controlDisable through external control or through DSG signal from the upper device in stack configurationtCTRDEG_ONEnable through external control or through the DSG signal from the upper device in stack configurationtCTRDEG_OFF
(1) These thresholds are target-based on temperature, but they are dependent on external components that could vary based on customer selections. The circuit is based on a 103AT NTC thermistor connected to TS and VSS, and a 10-kΩ resistor connected to VTB and TS. Actual thresholds are determined in mV; refers to the over- and undertemperature mV threshold in the Electrical Characteristics table.
Table 9-2 Cell Balancing Threshold Summary
NAMEDescriptionOptions
VSTARTStart threshold for cell balancing3.5 V, 3.8 V
VHYSTHysteresis between overvoltage and full charge voltage range (VOV – VFC)50 mV, 100 mV, 150 mV, 200 mV
VSTEPDifference between the cell balancing threshold voltages (VCBTH – VCBTL)50 mV, 100 mV, 150 mV, 200 mV