Cell balancing is performed by comparing the cell voltages with respect to cell balancing threshold voltages, evaluating the results of the comparison and controlling the cell balancing FET, which over a period of time will allow for closer cell voltages, thereby extending battery pack life. The conditions for performing cell balancing are: CBI is connected to VSS, no device in the stack is in a fault condition, and the pack is charging. The State Comparator section lists the conditions for the device's charging state.

CBI is the cell balancing input pin. It enables cell balancing function for the device.

• Leave the CBI pin floating to disable cell balancing. An internal circuit pulls up the CBI pin to AVDD in this case.
• Connect CBI to VSS to enable cell balancing.

In a single device, cell balancing of all the odd numbered cells can happen at the same time, and balancing of all the even numbered cells can also happen at the same time, but odd and even cells are not balanced at the same time. When devices are stacked on top of each other, verify in the PCB layout that the trace from VC5 pin to a cell and the trace from the VC0 pin of the next upper device to the immediately higher cell are kept separate.

All cell balancing FETs are turned off during voltage measurements. If odd numbered and even numbered cells need balancing at the same time, one single cycle time t_BAL is dedicated for odd numbered cells alone followed by the next t_BAL dedicated for even numbered cells alone. See an example of adjacent cell balancing in Figure 9-1.

Figure 9-1 Balancing Cells 1, 2, and 3

In a stacked configuration, the CBO pin of the bottom device must be connected to the CBI pin of the next upper device through a 10-kΩ resistor and so forth.

When a cell is in OV, its corresponding balancing FET is turned on if CBI is connected to VSS and if there are no discharge faults anywhere in the stack. The balancing FET is ON until the cell voltage drops to V_FC or V_OV – V_{HYS_OV}, whichever occurs earlier.

Figure 9-2 Cell-Balancing Algorithm

V_CBTL is the lower cell balancing threshold and V_CBTH is the upper cell balancing threshold. In Figure 9-2, the balancing FET is turned on only for the cell CV5. The BQ77915 V_START is set at 3.8 V; therefore, cell balancing starts only when individual cell voltages exceed 3.8 V. The difference between V_CBTH and V_CBTL can be programmed in the EEPROM to be between 50 mV and 200 mV, in steps of 50 mV. The difference between the V_OV and V_FC can also be programmed in the EEPROM to be between 50 mV and 200 mV, in steps of 50 mV.

When using the integrated MOSFETs for cell balancing, the cell monitor filter resistance R_INI controls the amount of cell balancing current the device can supply to the cells. Internal cell balancing should be used for cell balancing currents up to 50 mA. External MOSFETs have to be used if higher cell balancing currents are required. In the case of external balancing, the balancing current is controlled by the resistor R_CB in series with the external MOSFET, as shown in Figure 9-3. The pin filter resistance R_INE should be 1 kΩ and the capacitance C_INE should be 0.1 µF. The gate bias voltage necessary to turn on the FET connected to Cell(n) is generated by the resistor R_INE connected to the VC_(n–1) pin. The external MOSFET must be selected with a threshold voltage less than 1.7 V.

Figure 9-3 Cell Balancing with External MOSFETs