JAJSEZ9L march   2018  – august 2023 BQ77915

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 概要 (続き)
  7. 6 Device Comparison Table
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Device Functionality Summary
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Protection Summary
      2. 9.3.2  Fault Operation
        1. 9.3.2.1  Operation in OV
        2. 9.3.2.2  Operation in UV
        3. 9.3.2.3  Operation in OW
        4. 9.3.2.4  Operation in OCD1
        5. 9.3.2.5  Operation in OCD2
        6. 9.3.2.6  Programming the OCD1/2 Delay Using the OCDP Pin
        7. 9.3.2.7  Operation in SCD
        8. 9.3.2.8  Operation in OCC
        9. 9.3.2.9  Overcurrent Recovery Timer
        10. 9.3.2.10 Load Detection and Load Removal Detection
        11. 9.3.2.11 Operation in OTC
        12. 9.3.2.12 Operation in OTD
        13. 9.3.2.13 Operation in UTC
        14. 9.3.2.14 Operation in UTD
      3. 9.3.3  Protection Response and Recovery Summary
      4. 9.3.4  Cell Balancing
      5. 9.3.5  HIBERNATE Mode Operation
      6. 9.3.6  Configuration CRC Check and Comparator Built-In-Self-Test
      7. 9.3.7  Fault Detection Method
        1. 9.3.7.1 Filtered Fault Detection
      8. 9.3.8  State Comparator
      9. 9.3.9  DSG FET Driver Operation
      10. 9.3.10 CHG FET Driver Operation
      11. 9.3.11 External Override of CHG and DSG Drivers
      12. 9.3.12 Configuring 3-Series, 4-Series, or 5-Series Modes
      13. 9.3.13 Stacking Implementations
      14. 9.3.14 Zero-Volt Battery Charging Inhibition
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power Modes
        1. 9.4.1.1 Power On Reset (POR)
        2. 9.4.1.2 NORMAL Mode
        3. 9.4.1.3 FAULT Mode
        4. 9.4.1.4 HIBERNATE Mode
        5. 9.4.1.5 SHUTDOWN Mode
        6. 9.4.1.6 Customer Fast Production Test Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Recommended System Implementation
        1. 10.1.1.1 CHG and DSG FET Rise and Fall Time
        2. 10.1.1.2 Protecting CHG and LD
        3. 10.1.1.3 Protecting the CHG FET
        4. 10.1.1.4 Using Load Detect for UV Fault Recovery
        5. 10.1.1.5 Temperature Protection
        6. 10.1.1.6 Adding RC Filters to the Sense Resistor
        7. 10.1.1.7 Using the State Comparator in an Application
          1. 10.1.1.7.1 Examples
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Design Example
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 サード・パーティ製品に関する免責事項
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 用語集
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5 Electrical Characteristics

Typical values stated at TA = 25°C and VDD = 20 V. MIN and MAX values stated with TA = –40°C to 85°C and VDD = 3 to 25 V unless otherwise noted.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SUPPLY VOLTAGE
VPORPOR thresholdVDD rising, 0 to 6 V4V
VSHUTShutdown thresholdVDD falling, 6 to 0 V23.25V
VAVDDAVDD voltageCVDD = 1 µF2.13.6V
SUPPLY AND LEAKAGE CURRENT
ICCNORMAL mode currentCell1 through Cell5 = 4 V, VDD = 20 V, No cell balancing815µA
Cell balancing cells 3, 4 or 54880µA
IHIBHIBERNATE mode currentCell1 through Cell5 = 4 V, VDD = 20 V, HIBERNATE mode23μA
ICFAULTFault condition currentState comparator on1015µA
IOFFSHUTDOWN mode currentVDD < VSHUT, CTRC/CTRD floating0.5µA
ILKG_OW_DISInput leakage current at VCx pinsAll cell voltages = 4 V, open-wire disable configuration–1000100nA
ILKG_100nAOpen-wire sink current at VCx pinsAll cell voltages = 4 V, 100-nA configuration30110175nA
ILKG_200nAOpen-wire sink current at VCx pinsAll cell voltages = 4 V, 200-nA configuration95210315nA
ILKG_400nAOpen-wire sink current at VCx pinsAll cell voltages = 4 V, 400-nA configuration220425640nA
PROTECTION ACCURACIES
VOVOvervoltage programmable threshold range30004575mV
VUVUndervoltage programmable threshold range12003000mV
VVAOV, UV, detection accuracyTA = 25°C, OV detection accuracy–1010mV
TA = 25°C, UV detection accuracy–1818mV
TA = 0 to 60°C–2826mV
TA = –40 to +85°C–4040mV
VHYS_OVOV hysteresis programmable threshold range0400mV
VHYS_UVUV hysteresis programmable threshold range0800mV
VOTDOvertemperature in discharge programmable thresholdThreshold for 65°C based on a 10k pullup and 103AT thermistor19.69%20.56%21.86%VTB
Threshold for 70°C based on a 10k pullup and 103AT thermistor17.28%18.22%19.51%VTB
VOTD_RECOvertemperature in discharge recoveryRecovery threshold at 55°C for when VOTD is at 65°C based on a 10k pullup and 103AT thermistor25.18%26.12%27.44%VTB
Recovery threshold at 60°C for when VOTD is at 70°C based on a 10k pullup and 103AT thermistor22.05%23.2%
24.24%VTB
VOTCOvertemperature in charge programmable thresholdThreshold for 45°C based on a 10k pullup and 103AT thermistor32.14%32.94%34.54%VTB
Threshold for 50°C based on a 10k pullup and 103AT thermistor29.15%29.38%31.45%VTB
VOTC_RECOvertemperature in charge recoveryRecovery threshold at 35°C for when VOTD is at 45°C based on a 10k pullup and 103AT thermistor38.63%40.97%40.99%VTB
Recovery threshold at 40°C for when VOTD is at 50°C based on a 10k pullup and 103AT thermistor36.18%36.82%38.47%VTB
VUTDUndertemperature in discharge programmable thresholdThreshold for –20°C based on a 10k pullup and 103AT thermistor86.41%87.14%89.72%VTB
Threshold for –10°C based on a 10k pullup and 103AT thermistor80.04%80.94%83.10%VTB
VUTD_RECUndertemperature in discharge recoveryRecovery threshold at –10°C for when VUTD is at –20°C based on a 10k pullup and 103AT thermistor80.04%80.94%83.10%VTB
Recovery threshold at 0°C for when VUTD is at –10°C based on a 10k pullup and 103AT thermistor71.70%73.18%74.86%VTB
VUTCUndertemperature in charge programmable thresholdThreshold for –5°C based on a 10k pullup and 103AT thermistor75.06%77.22%78.32%VTB
Threshold for 0°C based on a 10k pullup and 103AT thermistor71.70%73.18%74.86%VTB
VUTC_RECUndertemperature in Charge RecoveryRecovery threshold at 5°C for when VUTC is at –5°C based on a 10k pullup and 103AT thermistor68.80%69.73%71.71%VTB
Recovery threshold at 10°C for when VUTC is at 0°C based on a 10k pullup and 103AT thermistor64.67%65.52%67.46%VTB
VOCCOvercurrent charge programmable threshold range, (VSRP-VSRN)
580mV
VOCD1Overcurrent discharge 1 programmable threshold range–85–10mV
VOCD2Overcurrent discharge 2 programmable threshold range–170–20mV
VSCDShort circuit discharge programmable threshold range–340–40mV
VCCALOCD1 detection accuracy at lower thresholdsVOCD1 ≤ 20 mV–30 %30 %
VCCAHOCC, OCD1, OCD2, SCD detection accuracyVOCD1 > 20 mV; all OCC, OCD2 and SCD threshold ranges–20 %20 %
VOWOpen-wire fault voltage threshold at VCx per cell with respect to VCx-1Voltage falling on VCx, 3.6 V to 0 V450500550mV
VOW_HYSHysteresis for open wire faultVoltage rising on VCx, 0 V to 3.6 V100mV
PROTECTION DELAYS
tOVn_DELAYOvervoltage detection delay time0.5-s delay option0.40.50.8s
1-s delay option0.811.4
2-s delay option1.822.7
4.5-s delay option44.55.2
tUVn_DELAYUndervoltage detection delay time1-s delay option0.811.5s
2-s delay option1.822.7
4.5-s delay option44.55.5
9-s delay option8910.2
tOWn_DELAYOpen-wire detection delay time3.64.55.3s
tOTC_DELAYOvertemperature charge detection delay time3.64.55.3s
tUTC_DELAYUndertemperature charge detection delay time3.64.55.3s
tOTD_DELAYOvertemperature discharge detection delay time3.64.55.3s
tUTD_DELAYUndertemperature discharge detection delay time3.64.55.3s
tOCD1_DELAYOvercurrent discharge 1 detection delay time10-ms delay option81015ms
20-ms delay option172026
45-ms delay option364552
90-ms delay option7890105
180-ms delay option155180205
350-ms delay option320350405
700-ms delay option640700825
1420-ms delay option129014201620
tOCD2_DELAYOvercurrent discharge 2 detection delay time5-ms delay option458ms
10-ms delay option81015
20-ms delay option172026
45-ms delay option364552
90-ms delay option7890105
180-ms delay option155180205
350-ms delay option320350405
700-ms delay option640700825
tSCD_DELAYShort-circuit detection delay time960-µs delay option5289601450us
tSCD_DELAYShort-circuit detection delay time400-µs delay option220400610µs
tOCC_DELAYOvercurrent charge detection delay time81012ms
tCD_RECOvercurrent discharge 1, Overcurrent discharge 2, Overcurrent charge and short-circuit recovery delay time250-ms option225250275ms
500-ms option450500550
CHARGE AND DISCHARGE FET DRIVERS
VFETONCHG/DSG onVDD ≥ 12 V, CL = 10 nF111214V
VDD < 12 V, CL = 10 nFVDD – 1.5VDDV
VFETOFFCHG/DSG off1-mA resistive load, CHG clamped to ground when CHG/DSG is off.0.5V
tCHGONCHG on rise timeCL = 10 nF, 10% to 90%50150µs
tDSGONDSG on rise timeCL = 10 nF, 10% to 90%275µs
tCHGOFFCHG off fall timeCL = 10 nF, 90% to 10%1530µs
tDSGOFFDSG off fall timeCL = 10 nF, 90% to 10%515µs
RCHGOFFCHG off resistanceCHG off and pin held at 2V0.30.50.75kΩ
RDSGOFFDSG off resistanceDSG off and pin held at 100 mV1016Ω
CELL BALANCING
VHYSTHysteresis between overvoltage and full charge voltage range (VOV – VFC, 4 steps of 50 mV)TA = 25°C50200mV
VSTEPDifference between the cell balancing threshold voltages (VCBTH – VCBTL, 4 steps of 50 mV)TA = 25°C50200mV
VCBILCBI low threshold0.5V
tCBI_DEGCBI deglitch period100ms
RBALCell balancing internal FET resistanceCell1 through Cell5 = 4 V, VDD = 20 V81220Ω
DBALCell balancing duty cycleOnly one cell balanced in the stack90 %
tBALOdd and even cell group balancing duration521ms
HIBERNATE MODE
VPRESHPRES High Threshold1.251.51.75V
tPRES_DEG_ENTPRES deglitch time (hibernate entry)4.5s
tPRES_DEG_EXTPRES deglitch time (hibernate exit)10ms
CTRC AND CTRD CONTROL
VCTR1Enable FET driver (VSS)With respect to VSS. Enabled < MAX0.6V
VCTR2Enable FET driver (Stacked)Enabled > MINVDD + 2.2V
VCTRDISDisable FET driverDisabled between MIN and MAX2.04VDD + 0.7V
VCTRMAXVCTRC and CTRD clamp voltageICTR = 600 nAVDD + 2.8VDD + 4VDD + 5V
tCTRDEG_ONCTRC and CTRD deglitch for ON signal8ms
tCTRDEG_OFFCTRC and CTRD deglitch for OFF signal8ms
CURRENT STATE COMPARATOR
VSTATE_DDischarge qualification threshold1Measured at SRP-SRN–1.875mV
VSTATE_D_HYSDischarge qualification threshold1 hysteresisMeasured at SRP-SRN–1.25mV
VSTATE_CCharge qualification threshold1Measured at SRP-SRN1.875mV
VSTATE_C_HYSCharge qualification threshold1 hysteresisMeasured at SRP-SRN1.25mV
tSTATEState detection qualification time1.2ms
LOAD DETECTION AND LOAD REMOVAL DETECTION
VLDCLAMPLD clamp voltageILDCLAMP = 300 µA161920V
ILDCLAMPLD clamp currentVLDCLAMP = 18 V450µA
VLDTLD thresholdOPEN pack terminals1.251.31.35V
RLD_INTLD input resistance when enabledMeasured to VSS200kΩ
tLD_DEGLD detection de-glitch11.52.3ms
CCFG PIN
VCCFGLCCFG threshold low (ratio of VAVDD)3-cell configuration10%AVDD
VCCFGHCCFG threshold high (ratio of VAVDD)4-cell configuration65%100%AVDD
VCCFGHZCFG threshold high-Z  (ratio of VAVDD)5-cell configuration, CCFG floating, internally biased25%33%45%AVDD
tCCFG_DEGCCFG deglitch6ms
CUSTOMER TEST MODE
VCTMCustomer test mode entry voltage at VDDVDD > VC5 + VCTM, TA = 25°C8.510V
tCTM_ENTRYDelay time to enter and exit customer test modeVDD > VC5 + VCTM, TA = 25°C50ms
tCTM_DELAYDelay time of faults while in customer test modeTA = 25°C200ms
tCTM_OC_RECFault recovery time of OCD1, OCD2, and SCD faults while in customer test mode250-ms and 500-ms options, TA = 25°C100ms