JAJSEZ9L march   2018  – august 2023 BQ77915

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 概要 (続き)
  7. 6 Device Comparison Table
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Device Functionality Summary
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Protection Summary
      2. 9.3.2  Fault Operation
        1. 9.3.2.1  Operation in OV
        2. 9.3.2.2  Operation in UV
        3. 9.3.2.3  Operation in OW
        4. 9.3.2.4  Operation in OCD1
        5. 9.3.2.5  Operation in OCD2
        6. 9.3.2.6  Programming the OCD1/2 Delay Using the OCDP Pin
        7. 9.3.2.7  Operation in SCD
        8. 9.3.2.8  Operation in OCC
        9. 9.3.2.9  Overcurrent Recovery Timer
        10. 9.3.2.10 Load Detection and Load Removal Detection
        11. 9.3.2.11 Operation in OTC
        12. 9.3.2.12 Operation in OTD
        13. 9.3.2.13 Operation in UTC
        14. 9.3.2.14 Operation in UTD
      3. 9.3.3  Protection Response and Recovery Summary
      4. 9.3.4  Cell Balancing
      5. 9.3.5  HIBERNATE Mode Operation
      6. 9.3.6  Configuration CRC Check and Comparator Built-In-Self-Test
      7. 9.3.7  Fault Detection Method
        1. 9.3.7.1 Filtered Fault Detection
      8. 9.3.8  State Comparator
      9. 9.3.9  DSG FET Driver Operation
      10. 9.3.10 CHG FET Driver Operation
      11. 9.3.11 External Override of CHG and DSG Drivers
      12. 9.3.12 Configuring 3-Series, 4-Series, or 5-Series Modes
      13. 9.3.13 Stacking Implementations
      14. 9.3.14 Zero-Volt Battery Charging Inhibition
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power Modes
        1. 9.4.1.1 Power On Reset (POR)
        2. 9.4.1.2 NORMAL Mode
        3. 9.4.1.3 FAULT Mode
        4. 9.4.1.4 HIBERNATE Mode
        5. 9.4.1.5 SHUTDOWN Mode
        6. 9.4.1.6 Customer Fast Production Test Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Recommended System Implementation
        1. 10.1.1.1 CHG and DSG FET Rise and Fall Time
        2. 10.1.1.2 Protecting CHG and LD
        3. 10.1.1.3 Protecting the CHG FET
        4. 10.1.1.4 Using Load Detect for UV Fault Recovery
        5. 10.1.1.5 Temperature Protection
        6. 10.1.1.6 Adding RC Filters to the Sense Resistor
        7. 10.1.1.7 Using the State Comparator in an Application
          1. 10.1.1.7.1 Examples
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Design Example
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 サード・パーティ製品に関する免責事項
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 用語集
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.3 Protection Response and Recovery Summary

Table 9-5 summarizes how each fault condition affects the state of the DSG and CHG output signals, as well as the recovery conditions required to resume charging and/or discharging. As a rule, the CHG and DSG output drivers are enabled only when no respective fault conditions are present. When multiple simultaneous faults (such as an OV and OTD) are present, all faults must be cleared before the FET can resume operation.

Table 9-5 Fault Condition, State, and Recovery Methods
FAULTFAULT TRIGGER CONDITIONCHGDSGRECOVERY METHODTRIGGER DELAYRECOVERY DELAY
CTRC disabledCTRC disabled for deglitch delay timeOFF—CTRC must be enabled for deglitch delay timetCTRDEG_ONtCTRDEG_OFF
CTRD disabledCTRD disabled for deglitch delay time—OFFCTRD must be enabled for deglitch delay time
OVV(Cell) rises above VOV for delay timeOFF—V(Cell) drops below VOV – VHYS_OV for delaytOVn_DELAY
UVV(Cell) drops below VUV for delay time—OFFDSG FET turned on after Load is removed and V(Cell) rises above VUV + VHYS_UV for delay.tUVn_DELAY
OWVCX – VCX–1 < VOW for delay timeOFFOFFBad VCX recovers such that VCX – VCX–1 > VOW + VOW_HYS for delaytOWn_DELAY
OCC(VSRP – VSRN) > VOCC for delay timeOFFOFFRecovery delay expires, OR
LD detects > VLDT, OR
Recovery delay expires + LD detects > VLDT		tOCC_DELAYtCD_REC
OCD1, OCD2, SCD(VSRP – VSRN) < VOCD1, VOCD2, or VSCD for delay timeOFFOFFRecovery delay expires, OR
LD detects < VLDT, OR
Recovery delay expires + LD detects < VLDT		tOCD1_DELAY, tOCD2_DELAY, tSCD_DELAYtCD_REC
OTC(1)Temperature rises above TOTC for delay timeOFF—Temp drops below TOTC – TOTC_REC for delaytOTC_DELAY
OTD(1)Temperature rises above TOTD for delay timeOFFOFFTemp drops below TOTD – TOTD_REC for delay, OR
Temp drops below TOTD – TOTD_REC for delay and Load is removed		tOTD_DELAY
UTC(1)Temperature drops below TUTC for delay timeOFF—Temperature rises above TUTC + TUTC_REC for delaytUTC_DELAY
UTD(1)Temp drops below TUTD for delay timeOFFOFFTemp rises above TUTD + TUTD_REC for delaytUTD_DELAY
(1) TUTC, TUTD, TUTC_REC, and TUTD_REC correspond to the temperature produced by VUTC, VUTD, VUTC_REC, and VUTD_REC of the selected thermistor resistance.

To prevent FET damage, there are times when the CHG FET or DSG FET may be enabled even though a fault event has occurred. See the State Comparator section for details.