JAJSGH5B August   2015  – November 2018

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: Supply Current
    6. 7.6  Electrical Characteristics: I/O
    7. 7.7  Electrical Characteristics: ADC
    8. 7.8  Electrical Characteristics: Power-On Reset
    9. 7.9  Electrical Characteristics: Oscillator
    10. 7.10 Electrical Characteristics: Data Flash Memory
    11. 7.11 Electrical Characteristics: Register Backup
    12. 7.12 SMBus Timing Specifications
    13. 7.13 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Primary (1st Level) Safety Features
      2. 8.3.2 Secondary (2nd Level) Safety Features
      3. 8.3.3 Charge Control Features
      4. 8.3.4 Fuel Gauging
      5. 8.3.5 Lifetime Data Logging
      6. 8.3.6 Authentication
      7. 8.3.7 Battery Parameter Measurements
        1. 8.3.7.1 Current and Coulomb Counting
        2. 8.3.7.2 Voltage
        3. 8.3.7.3 Temperature
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Physical Interface
      2. 8.5.2 SMBus Address
      3. 8.5.3 SMBus On and Off State
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Schematic
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Measurement System
          1. 9.2.3.1.1 Cell Voltages
          2. 9.2.3.1.2 External Average Cell Voltage
          3. 9.2.3.1.3 Current
          4. 9.2.3.1.4 Temperature
        2. 9.2.3.2 Gas Gauging
        3. 9.2.3.3 Charging
          1. 9.2.3.3.1 Fast Charging Voltage
          2. 9.2.3.3.2 Fast Charging Current
          3. 9.2.3.3.3 Other Charging Modes
        4. 9.2.3.4 Protection
        5. 9.2.3.5 Peripheral Features
          1. 9.2.3.5.1 LED Display
          2. 9.2.3.5.2 SMBus Address
      4. 9.2.4 Application Performance Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power Supply Decoupling Capacitor
      2. 11.1.2 MRST Connection
      3. 11.1.3 Communication Line Protection Components
      4. 11.1.4 ESD Spark Gap
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 関連資料
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

30-Pin DBT Package

Pin Functions

PIN NUMBER PIN NAME TYPE DESCRIPTION
1 COM O(1) Open-drain output LCD common connection. Leave unconnected if not used.
2 ALERT I Input from the bq769x0 AFE
3 SDA I/O Data transfer to and from the bq769x0 AFE. Requires a 10-k pullup to VCC
4 SCL I/O Communication clock to the bq769x0 AFE. Requires a 10-k pullup to VCC
5 PRECHG O Programmable polarity (default is active low) output to enable an optional precharge FET. This pin requires an external pullup to 2.5 V when configured as active high, and is open drain when configured as active low.
6 VAUX AI Auxiliary voltage input. If this pin is not used, then it should be tied to VSS.
7 BAT AI Translated battery voltage input
8 PRES I Active low input to sense system insertion. This typically requires additional ESD protection. If this pin is not used, then it should be tied to VSS.
9 KEYIN I A low level indicates application key-switch is inactive on position. A high level causes the DSG protection FET to open. If this pin is not used, then it should be tied to VSS.
10 SAFE O Active high output to enforce an additional level of safety protection (for example, fuse blow)
11 SMBD I/OD SMBus data open-drain bidirectional pin used to transfer an address and data to and from the bq78350-R1 device
12 VEN O Active high voltage translation enable. This open drain signal is used to switch the input voltage divider on/off to reduce the power consumption of the BAT translation divider network.
13 SMBC I/OD SMBus clock open-drain bidirectional pin used to clock the data transfer to and from the bq78350-R1 device
14 DISP I Display control for the LEDs. This pin is typically connected to bq78350-R1 device REGOUT via a 100-KΩ resistor and a push-button switch connect to VSS. Not used with LCD display enabled and can be tied to VSS.
15 PWRM O Power mode state indicator open drain output
16 LED1 O LED1/LCD1 display segment that drives an external LED/LCD, depending on the firmware configuration
17 LED2 O LED2/LCD2 display segment that drives an external LED/LCD, depending on the firmware configuration
18 LED3 O LED3/LCD3 display segment that drives an external LED/LCD, depending on the firmware configuration
19 LED4 O LED4/LCD4 display segment that drives an external LED/LCD, depending on the firmware configuration
20 LED5 O LED5/LCD5 display segment that drives an external LED/LCD, depending on the firmware configuration
21 GPIO A I/O Configurable Input or Output. If not used, tie to VSS.
22 VSS — Negative supply voltage
23 VSS — Negative supply voltage
24 MRST I Master reset input that forces the device into reset when held low. This pin must be held high for normal operation.
25 VSS — Negative supply voltage
26 VCC P Positive supply voltage
27 RBI P RAM backup input. Connect a capacitor to this pin and VSS to protect loss of RAM data in case of short circuit condition.
28 GPIO B I/O Configurable input or output. If not used, tie to VSS.
29 ADREN O Optional digital signal enables address detection measurement to reduce power consumption.
30 SMBA IA Optional SMBus address detection input. If this pin is not used, then it should be tied to VSS.
(1) I = Input, IA = Analog input, I/O = Input/output, I/OD = Input/Open-drain output, O = Output, OA = Analog output, P = Power