JAJSP77A November   2019  – August 2020 BQ79600-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 仕様
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Functional Modes and Power Supply
        1. 7.3.1.1 Power Mode
        2. 7.3.1.2 Pings
        3. 7.3.1.3 SPI/UART の選択
        4. 7.3.1.4 Digital Reset
        5. 7.3.1.5 Power Mode in BMS System
        6. 7.3.1.6 Power Supply
        7. 7.3.1.7 Shutdown
      2. 7.3.2 Communication
        1. 7.3.2.1 Data Communication Protocol
          1. 7.3.2.1.1 Frame Layer
            1. 7.3.2.1.1.1 Calculating Frame CRC Value
            2. 7.3.2.1.1.2 Verifying Frame CRC
          2. 7.3.2.1.2 Physical Layer
            1. 7.3.2.1.2.1 UART
              1. 7.3.2.1.2.1.1 TX HOLD OFF
              2. 7.3.2.1.2.1.2 UART COMM CLEAR
            2. 7.3.2.1.2.2 SPI
              1. 7.3.2.1.2.2.1 SPI_RDY と SPI FIFO
              2. 7.3.2.1.2.2.2 Flow to Read/Write BQ79600-Q1
              3. 7.3.2.1.2.2.3 SPI COMM CLEAR
            3. 7.3.2.1.2.3 Daisy Chain
        2. 7.3.2.2 Tone Communication Protocol
        3. 7.3.2.3 Device Auto Addressing / Ring Communication
          1. 7.3.2.3.1 Auto-Addressing
          2. 7.3.2.3.2 Ring Communication (optional)
        4. 7.3.2.4 Communication Timeout
        5. 7.3.2.5 Communication Debug Mode
      3. 7.3.3 Fault Handling
        1. 7.3.3.1 Fault Status Hierarchy/Reset/Mask
          1. 7.3.3.1.1 Fault Status Hierarchy
          2. 7.3.3.1.2 Fault Reset and Mask
        2. 7.3.3.2 Fault Interface
          1. 7.3.3.2.1 NFAULT
          2. 7.3.3.2.2 Daisy Chain (COMH and COML)
            1. 7.3.3.2.2.1 Fault Transmitting when BQ79600-Q1 in ACTIVE
            2. 7.3.3.2.2.2 Fault Transmitting when BQ79600-Q1 in SLEEP
            3. 7.3.3.2.2.3 Fault Transmitting (Automatic Host Wakeup/Reverse Wakeup) when BQ79600-Q1 in SHUTDOWN
      4. 7.3.4 INH/ Reverse Wakeup
      5. 7.3.5 Sniff Detector
      6. 7.3.6 Device Diagnostic
        1. 7.3.6.1 Power Supplies Check
          1. 7.3.6.1.1 Power Supply Diagnostic Check
          2. 7.3.6.1.2 Power Supply BIST
        2. 7.3.6.2 Thermal Shutdown
        3. 7.3.6.3 Oscillators Watchdog
        4. 7.3.6.4 Register Bit Flip Monitor
        5. 7.3.6.5 SPI FIFO 診断
    4. 7.4 Device Functional Modes
    5. 7.5 Register Maps
      1. 7.5.1  Register Summary Table
      2. 7.5.2  Register: DIR0_ADDR
      3. 7.5.3  Register: DIR1_ADDR
      4. 7.5.4  Register: CONTROL1
      5. 7.5.5  Register: CONTROL2
      6. 7.5.6  Register: DIAG_CTRL
      7. 7.5.7  Register: DEV_CONF1
      8. 7.5.8  Register: DEV_CONF2
      9. 7.5.9  Register: TX_HOLD_OFF
      10. 7.5.10 Register: SLP_TIMEOUT
      11. 7.5.11 Register: COMM_TIMEOUT
      12. 7.5.12 Register: SPI_FIFO_UNLOCK
      13. 7.5.13 Register: FAULT_MSK
      14. 7.5.14 Register: FAULT_RST
      15. 7.5.15 Register: FAULT_SUMMARY
      16. 7.5.16 Register: FAULT_REG
      17. 7.5.17 Register: FAULT_SYS
      18. 7.5.18 Register: FAULT_PWR
      19. 7.5.19 Register: FAULT_COMM1
      20. 7.5.20 Register: FAULT_COMM2
      21. 7.5.21 Register: DEV_DIAG_STAT
      22. 7.5.22 Register: PARTID
      23. 7.5.23 Register: DIE_ID1
      24. 7.5.24 Register: DIE_ID2
      25. 7.5.25 Register: DIE_ID3
      26. 7.5.26 Register: DIE_ID4
      27. 7.5.27 Register: DIE_ID5
      28. 7.5.28 Register: DIE_ID6
      29. 7.5.29 Register: DIE_ID7
      30. 7.5.30 Register: DIE_ID8
      31. 7.5.31 Register: DIE_ID9
      32. 7.5.32 Register: DEBUG_CTRL_UNLOCK
      33. 7.5.33 Register: DEBUG_COMM_CTRL
      34. 7.5.34 Register: DEBUG_COMM_STAT
      35. 7.5.35 Register: DEBUG_SPI_PHY
      36. 7.5.36 Register: DEBUG_SPI_FRAME
      37. 7.5.37 Register: DEBUG_UART_FRAME
      38. 7.5.38 Register: DEBUG_COMH_PHY
      39. 7.5.39 Register: DEBUG_COMH_FRAME
      40. 7.5.40 Register: DEBUG_COML_PHY
      41. 7.5.41 Register: DEBUG_COML_FRAME
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Bridge With Reverse Wakeup in UART
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 MCU Interface (UART, NFAULT)
          2. 8.2.1.2.2 Daisy Chain Interface
          3. 8.2.1.2.3 INH Connection
        3. 8.2.1.3 Application Performance Plot
      2. 8.2.2 Bridge Without Reverse Wakeup in SPI
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 MCU Interface (SPI, SPI_RDY, NFAULT)
          2. 8.2.2.2.2 Daisy Chain Interface
        3. 8.2.2.3 Application Performance Plot
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Ground Planes
      2. 10.1.2 Bypass Capacitors for Power Supplies
      3. 10.1.3 UART/SPI communication
      4. 10.1.4 Daisy Chain Communication
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Third-Party Products Disclaimer
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5.17 Register: FAULT_SYS

Address: 0x2102
B7B6B5B4B3B2B1B0
VALIDATE_DETLFOSHUTDOWN_RECDRSTCTLCTSTSHUTINH
00000000
RRRRRRRR
VALIDATE_DETIndicates device transitioned to VALIDATE mode
0: no transitioned to VALIDATE MODE
1: transitioned to VALIDATE MODE
LFOIndicated LFO frequency is off by +/-25%
0: no fault
1: fault
SHUTDOWN_RECIndicates the device was shut down using SHUTDOWN ping. If this bit is set, the COML and COMH RX are both disabled at wake up as a way to isolate itself from the stack. Send another wake ping or [SOFT_RESET] to re-enable COMH/L RX.
0: The previous SHUTDOWN was normal
1: The previous SHUTDOWN was caused by ping, which is not a usual SHUTDOWN method, indicating potential communication issue with the device
DRSTIndicates a digital reset has occurred.
0: no digital reset
1: digital reset has occurred
CTLIndicates a long communication timeout occurred. Device action is configured by [CTL_ACT]. This bit is not observable if the action is set to device shutdown.
0: No fault
1: long communication timeout occurs. Observable if long timeout action is set to SLEEP
CTSIndicates a short communication timeout occurred. No action from the device. This can be served as an alert to system before reaching long communication timeout.
0: No fault
1: short communication timeout occurs
TSHUTIndicates the previous shutdown was due to thermal shutdown
0: die temp is < thermal shutdown threshold
1: the previous shutdown was to due thermal shutdown
INHIndicates INH PMOS is enabled
0: INH driver is off
1: INH driver enabled, pulls pin up to BAT