JAJSP77A
November 2019 – August 2020
BQ79600-Q1
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
仕様
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Functional Modes and Power Supply
7.3.1.1
Power Mode
7.3.1.2
Pings
7.3.1.3
SPI/UART の選択
7.3.1.4
Digital Reset
7.3.1.5
Power Mode in BMS System
7.3.1.6
Power Supply
7.3.1.7
Shutdown
7.3.2
Communication
7.3.2.1
Data Communication Protocol
7.3.2.1.1
Frame Layer
7.3.2.1.1.1
Calculating Frame CRC Value
7.3.2.1.1.2
Verifying Frame CRC
7.3.2.1.2
Physical Layer
7.3.2.1.2.1
UART
7.3.2.1.2.1.1
TX HOLD OFF
7.3.2.1.2.1.2
UART COMM CLEAR
7.3.2.1.2.2
SPI
7.3.2.1.2.2.1
SPI_RDY と SPI FIFO
7.3.2.1.2.2.2
Flow to Read/Write BQ79600-Q1
7.3.2.1.2.2.3
SPI COMM CLEAR
7.3.2.1.2.3
Daisy Chain
7.3.2.2
Tone Communication Protocol
7.3.2.3
Device Auto Addressing / Ring Communication
7.3.2.3.1
Auto-Addressing
7.3.2.3.2
Ring Communication (optional)
7.3.2.4
Communication Timeout
7.3.2.5
Communication Debug Mode
7.3.3
Fault Handling
7.3.3.1
Fault Status Hierarchy/Reset/Mask
7.3.3.1.1
Fault Status Hierarchy
7.3.3.1.2
Fault Reset and Mask
7.3.3.2
Fault Interface
7.3.3.2.1
NFAULT
7.3.3.2.2
Daisy Chain (COMH and COML)
7.3.3.2.2.1
Fault Transmitting when BQ79600-Q1 in ACTIVE
7.3.3.2.2.2
Fault Transmitting when BQ79600-Q1 in SLEEP
7.3.3.2.2.3
Fault Transmitting (Automatic Host Wakeup/Reverse Wakeup) when BQ79600-Q1 in SHUTDOWN
7.3.4
INH/ Reverse Wakeup
7.3.5
Sniff Detector
7.3.6
Device Diagnostic
7.3.6.1
Power Supplies Check
7.3.6.1.1
Power Supply Diagnostic Check
7.3.6.1.2
Power Supply BIST
7.3.6.2
Thermal Shutdown
7.3.6.3
Oscillators Watchdog
7.3.6.4
Register Bit Flip Monitor
7.3.6.5
SPI FIFO 診断
7.4
Device Functional Modes
7.5
Register Maps
7.5.1
Register Summary Table
7.5.2
Register: DIR0_ADDR
7.5.3
Register: DIR1_ADDR
7.5.4
Register: CONTROL1
7.5.5
Register: CONTROL2
7.5.6
Register: DIAG_CTRL
7.5.7
Register: DEV_CONF1
7.5.8
Register: DEV_CONF2
7.5.9
Register: TX_HOLD_OFF
7.5.10
Register: SLP_TIMEOUT
7.5.11
Register: COMM_TIMEOUT
7.5.12
Register: SPI_FIFO_UNLOCK
7.5.13
Register: FAULT_MSK
7.5.14
Register: FAULT_RST
7.5.15
Register: FAULT_SUMMARY
7.5.16
Register: FAULT_REG
7.5.17
Register: FAULT_SYS
7.5.18
Register: FAULT_PWR
7.5.19
Register: FAULT_COMM1
7.5.20
Register: FAULT_COMM2
7.5.21
Register: DEV_DIAG_STAT
7.5.22
Register: PARTID
7.5.23
Register: DIE_ID1
7.5.24
Register: DIE_ID2
7.5.25
Register: DIE_ID3
7.5.26
Register: DIE_ID4
7.5.27
Register: DIE_ID5
7.5.28
Register: DIE_ID6
7.5.29
Register: DIE_ID7
7.5.30
Register: DIE_ID8
7.5.31
Register: DIE_ID9
7.5.32
Register: DEBUG_CTRL_UNLOCK
7.5.33
Register: DEBUG_COMM_CTRL
7.5.34
Register: DEBUG_COMM_STAT
7.5.35
Register: DEBUG_SPI_PHY
7.5.36
Register: DEBUG_SPI_FRAME
7.5.37
Register: DEBUG_UART_FRAME
7.5.38
Register: DEBUG_COMH_PHY
7.5.39
Register: DEBUG_COMH_FRAME
7.5.40
Register: DEBUG_COML_PHY
7.5.41
Register: DEBUG_COML_FRAME
8
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
Bridge With Reverse Wakeup in UART
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.2.1
MCU Interface (UART, NFAULT)
8.2.1.2.2
Daisy Chain Interface
8.2.1.2.3
INH Connection
8.2.1.3
Application Performance Plot
8.2.2
Bridge Without Reverse Wakeup in SPI
8.2.2.1
Design Requirements
8.2.2.2
Detailed Design Procedure
8.2.2.2.1
MCU Interface (SPI, SPI_RDY, NFAULT)
8.2.2.2.2
Daisy Chain Interface
8.2.2.3
Application Performance Plot
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.1.1
Ground Planes
10.1.2
Bypass Capacitors for Power Supplies
10.1.3
UART/SPI communication
10.1.4
Daisy Chain Communication
10.2
Layout Example
11
Device and Documentation Support
11.1
Device Support
11.2
Third-Party Products Disclaimer
11.3
Receiving Notification of Documentation Updates
11.4
Support Resources
11.5
Trademarks
11.6
静電気放電に関する注意事項
11.7
Glossary
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
PW|16
MPDS361A
サーマルパッド・メカニカル・データ
発注情報
jajsp77a_oa
jajsp77a_pm
7.3.3
Fault Handling