JAJSH94 April 2019 BQ79606A-Q1
PRODUCTION DATA.
COMM_UART_TR_STAT2 Register Address: 0x272 | |||||||
B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
SENTL[7] | SENTL[6] | SENTL[5] | SENTL[4] | SENTL[3] | SENTL[2] | SENTL[1] | SENTL[0] |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
R | R | R | R | R | R | R | R |
SENTL[7:0] | Low byte of the counter for response frames transmitted over the UART interface. Counter saturates when COMM_UART_TR_STAT1[SENTH] and COMM_UART_TR_STAT2[SENTL] reach 0xFFFF. The COMM_UART_*_STAT* registers are updated and the counters are reset when the COMM_UART_RC_STAT3 register is read to ensure all counter data refers to the same period of time. |