JAJSL83D
August 2020 – September 2022
BQ79612-Q1
,
BQ79614-Q1
,
BQ79616-Q1
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
概要 (続き)
6
Device Comparison Table
7
Pin Configuration and Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics
8.6
Timing Requirements
8.7
Typical Characteristics
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Power Supplies
9.3.1.1
AVAO_REF and AVDD_REF
9.3.1.2
LDOIN
9.3.1.3
AVDD
9.3.1.4
DVDD
9.3.1.5
CVDD and NEG5V
9.3.1.6
TSREF
9.3.2
Measurement System
9.3.2.1
Main ADC
9.3.2.1.1
Cell Voltage Measurements
9.3.2.1.1.1
Analog Front End
9.3.2.1.1.2
VC Channel Measurements
9.3.2.1.1.3
Post-ADC Digital LPF
9.3.2.1.1.4
BBP and BBN Measurements
9.3.2.1.2
Temperature Measurements
9.3.2.1.2.1
DieTemp1 Measurement
9.3.2.1.2.2
GPIOs and TSREF Measurements
9.3.2.1.3
Main ADC Operation Control
9.3.2.1.3.1
Operation Modes and Status
9.3.2.2
AUX ADC
9.3.2.2.1
AUX Cell Voltage Measurements
9.3.2.2.1.1
AUX Analog Front End
9.3.2.2.1.2
CB and BB Channel Measurements
9.3.2.2.2
AUX Temperature Measurements
9.3.2.2.2.1
DieTemp2 Measurement
9.3.2.2.2.2
AUX GPIO Measurements
9.3.2.2.3
MISC Measurements
9.3.2.2.4
AUX ADC Operation Control
9.3.2.3
Synchronization between MAIN and AUX ADC Measurements
9.3.3
Cell Balancing
9.3.3.1
Set Up Cell Balancing
9.3.3.1.1
Step 1: Determine Balancing Channels
9.3.3.1.2
Step 2: Select Balancing Control Methods
9.3.3.1.3
Step 3a: Balancing Thermal Management
9.3.3.1.4
Step 3b: Option to Stop On Cell Voltage Threshold
9.3.3.1.5
Step 3c: Option to Stop at Fault
9.3.3.2
Cell Balancing in SLEEP Mode
9.3.3.3
Pause and Stop Cell Balancing
9.3.3.3.1
Cell Balancing Pause
9.3.3.3.2
Cell Balancing Stop
9.3.3.3.3
Remaining CB Time
9.3.3.4
Module Balancing
9.3.3.4.1
Start Module Balancing
9.3.3.4.2
Stop Module Balancing
9.3.4
Integrated Hardware Protectors
9.3.4.1
OVUV Protectors
9.3.4.1.1
OVUV Operation Modes
9.3.4.1.2
OVUV Control and Status
9.3.4.1.2.1
OVUV Control
9.3.4.1.2.2
OVUV Status
9.3.4.2
OTUT Protector
9.3.4.2.1
OTUT Operation Modes
9.3.4.2.2
OTUT Control and Status
9.3.4.2.2.1
OTUT Control
9.3.4.2.2.2
OTUT Status
9.3.5
GPIO Configuration
9.3.6
Communication, OTP, Diagnostic Control
9.3.6.1
Communication
9.3.6.1.1
Serial Interface
9.3.6.1.1.1
UART Physical Layer
9.3.6.1.1.1.1
UART Transmitter
9.3.6.1.1.1.2
UART Receiver
9.3.6.1.1.1.3
COMM CLEAR
9.3.6.1.1.2
Command and Response Protocol
9.3.6.1.1.2.1
Transaction Frame Structure
9.3.6.1.1.2.1.1
Frame Initialization Byte
9.3.6.1.1.2.1.2
Device Address Byte
9.3.6.1.1.2.1.3
Register Address Bytes
9.3.6.1.1.2.1.4
Data Bytes
9.3.6.1.1.2.1.5
CRC Bytes
9.3.6.1.1.2.1.6
Calculating Frame CRC Value
9.3.6.1.1.2.1.7
Verifying Frame CRC
9.3.6.1.1.2.2
Transaction Frame Examples
9.3.6.1.1.2.2.1
Single Device Read/Write
9.3.6.1.1.2.2.2
Stack Read/Write
9.3.6.1.1.2.2.3
Broadcast Read/Write
9.3.6.1.1.2.2.4
Broadcast Write Reverse Direction
9.3.6.1.2
Daisy Chain Interface
9.3.6.1.2.1
Daisy Chain Transmitter and Receiver Functionality
9.3.6.1.2.2
Daisy Chain Protocol
9.3.6.1.3
Start Communication
9.3.6.1.3.1
Identify Base and Stack
9.3.6.1.3.2
Auto-Addressing
9.3.6.1.3.2.1
Setting Up the Device Addresses
9.3.6.1.3.2.2
Setting Up COMM_CTRL[STACK_DEV] and [TOP_STACK]
9.3.6.1.3.2.3
Storing Device Address to OTP
9.3.6.1.3.3
Synchronize Daisy Chain DLL
9.3.6.1.3.4
Ring Communication
9.3.6.1.4
Communication Timeout
9.3.6.1.4.1
Short Communication Timeout
9.3.6.1.4.2
Long Communication Timeout
9.3.6.1.5
Communication Debug Mode
9.3.6.1.6
Multidrop Configuration
9.3.6.1.7
SPI Master
9.3.6.1.8
SPI Loopback
9.3.6.2
Fault Handling
9.3.6.2.1
Fault Status Hierarchy
9.3.6.2.1.1
Debug Registers
9.3.6.2.2
Fault Masking and Reset
9.3.6.2.2.1
Fault Masking
9.3.6.2.2.2
Fault Reset
9.3.6.2.3
Fault Signaling
9.3.6.2.3.1
Fault Status Transmitting in ACTIVE Mode
9.3.6.2.3.2
Fault Status Transmitting in SLEEP Mode
9.3.6.2.3.3
Heartbeat and Fault Tone
9.3.6.3
Nonvolatile Memory
9.3.6.3.1
OTP Page Status
9.3.6.3.2
OTP Programming
9.3.6.4
Diagnostic Control/Status
9.3.6.4.1
Power Supplies Check
9.3.6.4.1.1
Power Supply Diagnostic Check
9.3.6.4.1.2
Power Supply BIST
9.3.6.4.2
Thermal Shutdown and Warning Check
9.3.6.4.2.1
Thermal Shutdown
9.3.6.4.2.2
Thermal Warning
9.3.6.4.3
Oscillators Watchdog
9.3.6.4.4
OTP Error Check
9.3.6.4.4.1
OTP CRC Test and Faults
9.3.6.4.4.2
OTP Margin Read
9.3.6.4.4.3
Error Check and Correct (ECC) OTP
9.3.6.4.5
Integrated Hardware Protector Check
9.3.6.4.5.1
Parity Check
9.3.6.4.5.2
OVUV and OTUT DAC Check
9.3.6.4.5.3
OVUV Protector BIST
9.3.6.4.5.4
OTUT Protector BIST
9.3.6.4.6
Diagnostic Through ADC Comparison
9.3.6.4.6.1
Cell Voltage Measurement Check
9.3.6.4.6.2
Temperature Measurement Check
9.3.6.4.6.3
Cell Balancing FETs Check
9.3.6.4.6.4
VC and CB Open Wire Check
9.3.7
Bus Bar Support
9.3.7.1
Bus Bar on BBP/BBN Pins
9.3.7.1.1
Typical Connection
9.3.7.1.2
Bus Bar Measurement
9.3.7.1.3
Cell Balancing Handling
9.3.7.1.4
Cell Voltage Diagnostic Control
9.3.7.2
Bus Bar on Individual VC Channel
9.3.7.2.1
Typical Connection
9.3.7.2.2
Bus Bar Measurement
9.3.7.2.3
Cell Balancing Handling
9.3.7.2.4
Cell Voltage Diagnostic Control
9.4
Device Functional Modes
9.4.1
Power Modes
9.4.1.1
SHUTDOWN Mode
9.4.1.1.1
Exit SHUTDOWN Mode
9.4.1.1.2
Enter SHUTDOWN Mode
9.4.1.2
SLEEP Mode
9.4.1.2.1
Exit SLEEP Mode
9.4.1.2.2
Enter SLEEP Mode
9.4.1.3
ACTIVE Mode
9.4.1.3.1
Exit ACTIVE Mode
9.4.1.3.2
Enter ACTIVE Mode From SHUTDOWN Mode
9.4.1.3.3
Enter ACTIVE Mode From SLEEP Mode
9.4.2
Device Reset
9.4.3
Ping and Tone
9.4.3.1
Ping
9.4.3.2
Tone
9.4.3.3
Ping and Tone Propagation
9.5
Register Maps
9.5.1
OTP Shadow Register Summary
9.5.2
Read/Write Register Summary
9.5.3
Read-Only Register Summary
9.5.4
Register Field Descriptions
9.5.4.1
Device Addressing Setup
9.5.4.1.1
DIR0_ADDR_OTP
9.5.4.1.2
DIR1_ADDR_OTP
9.5.4.1.3
CUST_MISC1 through CUST_MISC8
9.5.4.1.4
DIR0_ADDR
9.5.4.1.5
DIR1_ADDR
9.5.4.2
Device ID and Scratch Pad
9.5.4.2.1
PARTID
9.5.4.2.2
DEV_REVID
9.5.4.2.3
DIE_ID1 through DIE_ID9
9.5.4.3
General Configuration and Control
9.5.4.3.1
DEV_CONF
9.5.4.3.2
ACTIVE_CELL
9.5.4.3.3
BBVC_POSN1
9.5.4.3.4
BBVC_POSN2
9.5.4.3.5
PWR_TRANSIT_CONF
9.5.4.3.6
COMM_TIMEOUT_CONF
9.5.4.3.7
TX_HOLD_OFF
9.5.4.3.8
STACK_RESPONSE
9.5.4.3.9
BBP_LOC
9.5.4.3.10
COMM_CTRL
9.5.4.3.11
CONTROL1
9.5.4.3.12
CONTROL2
9.5.4.3.13
CUST_CRC_HI
9.5.4.3.14
CUST_CRC_LO
9.5.4.3.15
CUST_CRC_RSLT_HI
9.5.4.3.16
CUST_CRC_RSLT_LO
9.5.4.4
Operation Status
9.5.4.4.1
DIAG_STAT
9.5.4.4.2
ADC_STAT1
9.5.4.4.3
ADC_STAT2
9.5.4.4.4
GPIO_STAT
9.5.4.4.5
BAL_STAT
9.5.4.4.6
DEV_STAT
9.5.4.5
ADC Configuration and Control
9.5.4.5.1
ADC_CONF1
9.5.4.5.2
ADC_CONF2
9.5.4.5.3
MAIN_ADC_CAL1
9.5.4.5.4
MAIN_ADC_CAL2
9.5.4.5.5
AUX_ADC_CAL1
9.5.4.5.6
AUX_ADC_CAL2
9.5.4.5.7
ADC_CTRL1
9.5.4.5.8
ADC_CTRL2
9.5.4.5.9
ADC_CTRL3
9.5.4.6
ADC Measurement Results
9.5.4.6.1
VCELL16_HI/LO
9.5.4.6.2
VCELL15_HI/LO
9.5.4.6.3
VCELL14_HI/LO
9.5.4.6.4
VCELL13_HI/LO
9.5.4.6.5
VCELL12_HI/LO
9.5.4.6.6
VCELL11_HI/LO
9.5.4.6.7
VCELL10_HI/LO
9.5.4.6.8
VCELL9_HI/LO
9.5.4.6.9
VCELL8_HI/LO
9.5.4.6.10
VCELL7_HI/LO
9.5.4.6.11
VCELL6_HI/LO
9.5.4.6.12
VCELL5_HI/LO
9.5.4.6.13
VCELL4_HI/LO
9.5.4.6.14
VCELL3_HI/LO
9.5.4.6.15
VCELL2_HI/LO
9.5.4.6.16
VCELL1_HI/LO
9.5.4.6.17
BUSBAR_HI/LO
9.5.4.6.18
TSREF_HI/LO
9.5.4.6.19
GPIO1_HI/LO
9.5.4.6.20
GPIO2_HI/LO
9.5.4.6.21
GPIO3_HI/LO
9.5.4.6.22
GPIO4_HI/LO
9.5.4.6.23
GPIO5_HI/LO
9.5.4.6.24
GPIO6_HI/LO
9.5.4.6.25
GPIO7_HI/LO
9.5.4.6.26
GPIO8_HI/LO
9.5.4.6.27
DIETEMP1_HI/LO
9.5.4.6.28
DIETEMP2_HI/LO
9.5.4.6.29
AUX_CELL_HI/LO
9.5.4.6.30
AUX_GPIO_HI/LO
9.5.4.6.31
AUX_BAT_HI/LO
9.5.4.6.32
AUX_REFL_HI/LO
9.5.4.6.33
AUX_VBG2_HI/LO
9.5.4.6.34
AUX_AVAO_REF_HI/LO
9.5.4.6.35
AUX_AVDD_REF_HI/LO
9.5.4.6.36
AUX_OV_DAC_HI/LO
9.5.4.6.37
AUX_UV_DAC_HI/LO
9.5.4.6.38
AUX_OT_OTCB_DAC_HI/LO
9.5.4.6.39
AUX_UT_DAC_HI/LO
9.5.4.6.40
AUX_VCBDONE_DAC_HI/LO
9.5.4.6.41
AUX_VCM_HI/LO
9.5.4.6.42
REFOVDAC_HI/LO
9.5.4.6.43
DIAG_MAIN_HI/LO
9.5.4.6.44
DIAG_AUX_HI/LO
9.5.4.7
Balancing Configuration, Control and Status
9.5.4.7.1
CB_CELL16_CTRL through CB_CELL1_CTRL
9.5.4.7.2
VMB_DONE_THRESH
9.5.4.7.3
MB_TIMER_CTRL
9.5.4.7.4
VCB_DONE_THRESH
9.5.4.7.5
OTCB_THRESH
9.5.4.7.6
BAL_CTRL1
9.5.4.7.7
BAL_CTRL2
9.5.4.7.8
BAL_CTRL3
9.5.4.7.9
CB_COMPLETE1
9.5.4.7.10
CB_COMPLETE2
9.5.4.7.11
BAL_TIME
9.5.4.8
Protector Configuration and Control
9.5.4.8.1
OV_THRESH
9.5.4.8.2
UV_THRESH
9.5.4.8.3
UV_DISABLE1
9.5.4.8.4
UV_DISABLE2
9.5.4.8.5
OTUT_THRESH
9.5.4.8.6
OVUV_CTRL
9.5.4.8.7
OTUT_CTRL
9.5.4.9
GPIO Configuration
9.5.4.9.1
GPIO_CONF1
9.5.4.9.2
GPIO_CONF2
9.5.4.9.3
GPIO_CONF3
9.5.4.9.4
GPIO_CONF4
9.5.4.10
SPI Master
9.5.4.10.1
SPI_CONF
9.5.4.10.2
SPI_EXE
9.5.4.10.3
SPI_TX3, SPI_TX2, and SPI_TX1
9.5.4.10.4
SPI_RX3, SPI_RX2, and SPI_RX1
9.5.4.11
Diagnostic Control
9.5.4.11.1
DIAG_OTP_CTRL
9.5.4.11.2
DIAG_COMM_CTRL
9.5.4.11.3
DIAG_PWR_CTRL
9.5.4.11.4
DIAG_CBFET_CTRL1
9.5.4.11.5
DIAG_CBFET_CTRL2
9.5.4.11.6
DIAG_COMP_CTRL1
9.5.4.11.7
DIAG_COMP_CTRL2
9.5.4.11.8
DIAG_COMP_CTRL3
9.5.4.11.9
DIAG_COMP_CTRL4
9.5.4.11.10
DIAG_PROT_CTRL
9.5.4.12
Fault Configuration and Reset
9.5.4.12.1
FAULT_MSK1
9.5.4.12.2
FAULT_MSK2
9.5.4.12.3
FAULT_RST1
9.5.4.12.4
FAULT_RST2
9.5.4.13
Fault Status
9.5.4.13.1
FAULT_SUMMARY
9.5.4.13.2
FAULT_COMM1
9.5.4.13.3
FAULT_COMM2
9.5.4.13.4
FAULT_COMM3
9.5.4.13.5
FAULT_OTP
9.5.4.13.6
FAULT_SYS
9.5.4.13.7
FAULT_PROT1
9.5.4.13.8
FAULT_PROT2
9.5.4.13.9
FAULT_OV1
9.5.4.13.10
FAULT_OV2
9.5.4.13.11
FAULT_UV1
9.5.4.13.12
FAULT_UV2
9.5.4.13.13
FAULT_OT
9.5.4.13.14
FAULT_UT
9.5.4.13.15
FAULT_COMP_GPIO
9.5.4.13.16
FAULT_COMP_VCCB1
9.5.4.13.17
FAULT_COMP_VCCB2
9.5.4.13.18
FAULT_COMP_VCOW1
9.5.4.13.19
FAULT_COMP_VCOW2
9.5.4.13.20
FAULT_COMP_CBOW1
9.5.4.13.21
FAULT_COMP_CBOW2
9.5.4.13.22
FAULT_COMP_CBFET1
9.5.4.13.23
FAULT_COMP_CBFET2
9.5.4.13.24
FAULT_COMP_MISC
9.5.4.13.25
FAULT_PWR1
9.5.4.13.26
FAULT_PWR2
9.5.4.13.27
FAULT_PWR3
9.5.4.14
Debug Control and Status
9.5.4.14.1
DEBUG_CTRL_UNLOCK
9.5.4.14.2
DEBUG_COMM_CTRL1
9.5.4.14.3
DEBUG_COMM_CTRL2
9.5.4.14.4
DEBUG_COMM_STAT
9.5.4.14.5
DEBUG_UART_RC
9.5.4.14.6
DEBUG_UART_RR_TR
9.5.4.14.7
DEBUG_COMH_BIT
9.5.4.14.8
DEBUG_COMH_RC
9.5.4.14.9
DEBUG_COMH_RR_TR
9.5.4.14.10
DEBUG_COML_BIT
9.5.4.14.11
DEBUG_COML_RC
9.5.4.14.12
DEBUG_COML_RR_TR
9.5.4.14.13
DEBUG_UART_DISCARD
9.5.4.14.14
DEBUG_COMH_DISCARD
9.5.4.14.15
DEBUG_COML_DISCARD
9.5.4.14.16
DEBUG_UART_VALID_HI/LO
9.5.4.14.17
DEBUG_COMH_VALID_HI/LO
9.5.4.14.18
DEBUG_COML_VALID_HI/LO
9.5.4.14.19
DEBUG_OTP_SEC_BLK
9.5.4.14.20
DEBUG_OTP_DED_BLK
9.5.4.15
OTP Programming Control and Status
9.5.4.15.1
OTP_PROG_UNLOCK1A through OTP_PROG_UNLOCK1D
9.5.4.15.2
OTP_PROG_UNLOCK2A through OTP_PROG_UNLOCK2D
9.5.4.15.3
OTP_PROG_CTRL
9.5.4.15.4
OTP_ECC_TEST
9.5.4.15.5
OTP_ECC_DATAIN1 through OTP_ECC_DATAIN9
9.5.4.15.6
OTP_ECC_DATAOUT1 through OTP_ECC_DATAOUT9
9.5.4.15.7
OTP_PROG_STAT
9.5.4.15.8
OTP_CUST1_STAT
9.5.4.15.9
OTP_CUST2_STAT
10
Application and Implementation
10.1
Application Information
10.2
Typical Applications
10.2.1
Base Device Application Circuit
10.2.1.1
Design Requirements
10.2.1.2
Detailed Design Procedure
10.2.1.2.1
Cell Sensing and Balancing Inputs
10.2.1.2.2
BAT and External NPN
10.2.1.2.3
Power Supplies, Reference Input
10.2.1.2.4
GPIO For Thermistor Inputs
10.2.1.2.5
Internal Balancing Current
10.2.1.2.6
UART, NFAULT
10.2.1.2.7
Daisy Chain Isolation
10.2.1.2.7.1
Devices Connected on the Same PCB
10.2.1.2.7.2
Devices Connected on Different PCBs
10.2.1.3
Application Curve
10.2.2
Daisy Device Application Circuit
10.2.2.1
Design Requirements
10.2.2.2
Detailed Design Procedure
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.1.1
Ground Planes
12.1.2
Bypass Capacitors for Power Supplies and Reference
12.1.3
Cell Voltage Sensing
12.1.4
Daisy Chain Communication
12.2
Layout Example
13
Device and Documentation Support
13.1
Device Support
13.1.1
Third-Party Products Disclaimer
13.2
Receiving Notification of Documentation Updates
13.3
サポート・リソース
13.4
Trademarks
13.5
Electrostatic Discharge Caution
13.6
Glossary
14
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
PAP|64
MPQF071C
サーマルパッド・メカニカル・データ
PAP|64
PPTD012N
発注情報
jajsl83d_oa
jajsl83d_pm
9.5.4.2
Device ID and Scratch Pad