JAJSEK1C August   2011  – August 2018 BUF20800-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック概略図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 General-call Reset and Power-up
      2. 7.3.2 Output Voltage
      3. 7.3.3 Output Latch
      4. 7.3.4 Programmable VCOM
      5. 7.3.5 REFH and REFL Input range
    4. 7.4 Device Functional Modes
      1. 7.4.1 Replacement of Traditional Gamma Buffer
      2. 7.4.2 Dynamic Gamma Control
    5. 7.5 Programming
      1. 7.5.1 Two-wire Bus Overview
      2. 7.5.2 Data Rates
      3. 7.5.3 Read/Write Operations
        1. 7.5.3.1 Writing
        2. 7.5.3.2 Reading
      4. 7.5.4 Register Maps
        1. 7.5.4.1 Addressing the BUF20800-Q1
      5. 7.5.5 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor Selection
        2. 8.2.2.2 REFH and REFL Voltage Settings
      3. 8.2.3 Application Curves
      4. 8.2.4 Configuration for 20 Gamma Channels
      5. 8.2.5 Configuration for 22 Gamma Channels
      6. 8.2.6 The BUF20800-Q1 in Industrial Applications
      7. 8.2.7 Total TI Panel Solution
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General PowerPAD Design Considerations
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.3 Output Latch

Updating the DAC register is not the same as updating the DAC output voltage, because the BUF20800-Q1 features a double-buffered register structure. There are three methods for latching transferred data from the storage registers into the DACs to update the DAC output voltages.

Method 1 requires externally setting the latch pin (LD) LOW, LD = LOW, which will update each DAC output voltage whenever its corresponding register is updated.

Method 2 externally sets LD = HIGH to allow all DAC output voltages to retain their values during data transfer and until LD = LOW, which will then simultaneously update the output voltages of all DACs to the new register values. Use this method to transfer a future data set in advance to prepare for a very fast output voltage update.

Method 3 uses software control. LD is maintained HIGH, and all DACs are updated when the master writes a 1 in bit 15 of any DAC register. The update will occur after receiving the 16-bit data for the currently-written register.

The General Call Reset and the power-up reset will update the DAC regardless of the state of the latch pin.