JAJSEK1C August   2011  – August 2018 BUF20800-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック概略図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 General-call Reset and Power-up
      2. 7.3.2 Output Voltage
      3. 7.3.3 Output Latch
      4. 7.3.4 Programmable VCOM
      5. 7.3.5 REFH and REFL Input range
    4. 7.4 Device Functional Modes
      1. 7.4.1 Replacement of Traditional Gamma Buffer
      2. 7.4.2 Dynamic Gamma Control
    5. 7.5 Programming
      1. 7.5.1 Two-wire Bus Overview
      2. 7.5.2 Data Rates
      3. 7.5.3 Read/Write Operations
        1. 7.5.3.1 Writing
        2. 7.5.3.2 Reading
      4. 7.5.4 Register Maps
        1. 7.5.4.1 Addressing the BUF20800-Q1
      5. 7.5.5 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor Selection
        2. 8.2.2.2 REFH and REFL Voltage Settings
      3. 8.2.3 Application Curves
      4. 8.2.4 Configuration for 20 Gamma Channels
      5. 8.2.5 Configuration for 22 Gamma Channels
      6. 8.2.6 The BUF20800-Q1 in Industrial Applications
      7. 8.2.7 Total TI Panel Solution
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General PowerPAD Design Considerations
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5.4.1 Addressing the BUF20800-Q1

The address of the BUF20800-Q1 is 111010x, where x is the state of the A0 pin. When the A0 pin is LOW, the device will acknowledge on address 74h (1110100). If the A0 pin is HIGH, the device will acknowledge on address 75h (1110101).

Other valid addresses are possible through a simple mask change. Contact your TI representative for information.

Table 1. Quick-Reference Table of BUF20800-Q1 Addresses

DEVICE/COMPONENT
BUF20800-Q1 Address: ADDRESS
A0 pin is LOW
(device acknowledges on address 74h)		 1110100
A0 pin is HIGH
(device acknowledges on address 75h)		 1110101

Table 2. Quick-Reference Table of Command Codes

COMMAND CODE
General Call Reset Address byte of 00h followed by a data byte of 06h.
High-Speed Mode 00001xxx, with SCL ≤ 400kHz; where xxx are bits unique to the Hs-capable master. This byte is called the Hs master code.