JAJSMA5C June   2021  – March 2022 BUF802

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 説明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: Wide Bandwidth Mode
    6. 6.6 Electrical Characteristics: Low Quiescent Current Mode
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input and Output Over-Voltage Clamp
      2. 8.3.2 Adjustable Quiescent Current
      3. 8.3.3 ESD Structure
    4. 8.4 Device Functional Modes
      1. 8.4.1 Buffer Mode (BF Mode)
      2. 8.4.2 Composite Loop Mode (CL Mode)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Oscilloscope Front-End Amplifier Design
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Transforming a Wide-Bandwidth, 50 Ω Input Signal Chain to High-Input Impedance
        1. 9.2.2.1 Detailed Design Results
        2. 9.2.2.2 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 Typical Characteristics

At TA = 25°C, VS = ±6 V, RL = 100 Ω || 400 fF, RS = 25 Ω, VOCM = 0 V (mid-supply), VOUT = 1 VPP, CLH and CLL tied to VS+ and VS- respectively, Wide Bandwidth Mode unless otherwise specified (R_Bias = 17.8 kΩ).

Wide Bandwidth Mode
Figure 6-1 Frequency Response vs Output Voltage
Wide Bandwidth Mode
Figure 6-3 Frequency Response vs Output Voltage,
0.1 dB Flatness
Figure 6-5 Frequency Response vs Output Load
Figure 6-7 Frequency Response vs Capacitive Load
Rising edge, VOUT = 1.2 VPP
Figure 6-9 Large-Signal Transient Response
Rising edge, VOUT = 250 mVPP
Figure 6-11 Small-Signal Transient Response
VOUT = 1 VPP
Figure 6-13 Harmonic Distortion vs Frequency
f = 500 MHz
Figure 6-15 Harmonic Distortion vs Supply Voltage
f = 1 GHz
Figure 6-17 Harmonic Distortion vs Output Voltage
Figure 6-19 Voltage and Current Noise Density vs Frequency
Figure 6-21 Input Impedance vs Frequency
μ = 3.1 pA, σ = 1.03 pA
Figure 6-23 Input Bias Current Distribution
Figure 6-25 Input Bias Current vs Input Common Mode Voltage
μ = 0.971 V/V, σ = 0.000485 V/V
Figure 6-27 DC Gain Histogram
μ = 587.668 mV, σ = 8.80778 mV
Figure 6-29 Offset Voltage Histogram
Figure 6-31 Transient Clamp Response
Low Quiescent Current Mode
Figure 6-2 Frequency Response vs Output Voltage
Figure 6-4 Frequency Response vs Supply Voltage
Figure 6-6 Frequency Response vs R_Bias Resistance
Figure 6-8 Frequency Response vs Cap Load with Recommended RISO
Falling edge, VOUT = 1.2 VPP
Figure 6-10 Large-Signal Transient Response
Falling edge, VOUT = 250 mVPP
Figure 6-12 Small-Signal Transient Response
VOUT = 2 VPP
Figure 6-14 Harmonic Distortion vs Frequency
Figure 6-16 Harmonic Distortion vs Output Common Mode Voltage
f = 1 GHz
Figure 6-18 Harmonic Distortion vs Output Load
With RC pole of 2 kΩ and 10 pF at IN_Aux pin
Figure 6-20 Auxiliary Path Frequency Response
Figure 6-22 Output Impedance vs Frequency
40 units
Figure 6-24 Input Bias Current vs Temperature
Wide Bandwdith Mode and Low IQ Mode
Figure 6-26 Quiescent Current vs Temperature
Normalized to 25 °C values, 40 units
Figure 6-28 DC Gain vs Temperature
Normalized to 25 °C values, 40 units
Figure 6-30 Offset Voltage vs Temperature
Figure 6-32 Clamp Voltage Error Histogram