JAJSMA5C June   2021  – March 2022 BUF802

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 説明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: Wide Bandwidth Mode
    6. 6.6 Electrical Characteristics: Low Quiescent Current Mode
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input and Output Over-Voltage Clamp
      2. 8.3.2 Adjustable Quiescent Current
      3. 8.3.3 ESD Structure
    4. 8.4 Device Functional Modes
      1. 8.4.1 Buffer Mode (BF Mode)
      2. 8.4.2 Composite Loop Mode (CL Mode)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Oscilloscope Front-End Amplifier Design
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Transforming a Wide-Bandwidth, 50 Ω Input Signal Chain to High-Input Impedance
        1. 9.2.2.1 Detailed Design Results
        2. 9.2.2.2 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-20210112-CA0I-V2CL-FBGD-D6SZNF8BD5C6-low.gif Figure 5-1 RGT Package, 16-Pin VQFN
(Top View and Bottom View)
Table 5-1 Pin Functions
PIN TYPE(4) Operating Mode(1)(2) DESCRIPTION
NAME NO.
Aux_Bias 6 P CL Connect to VS- to enable control of OUT through the In_Aux.
CLH 15 I BF, CL Input pin for setting positive clamp voltage
CLL 14 I BF, CL Input pin for setting negative clamp voltage
IN 2 I BF, CL Signal input
In_Aux 4 I CL Auxiliary input for controlling OUT through an external amplifier.
In_Bias 3 I CL JFET biasing pin
NC 16, 13, 9 — — Do not connect.
OUT 11 O BF, CL Signal output
R_Bias 7 I BF, CL Output stage bias current setting pin
VS+ 1 P BF, CL Positive power supply connection for Input Stage.
VS- 5, 8 P BF, CL Negative power supply connection for Input Stage. Pin 5 and Pin 8 are internally shorted.
VSO+(3) 12 P BF, CL Positive power supply connection for Output Stage.
VSO-(3) 10 P BF, CL Negative power supply connection for Output Stage.
Thermal Pad — — The thermal pad is electrically isolated from the die and pins. Connect the thermal pad to any potential.
(1) See Section 8.4 for more information on Buffer Mode (BF) and Composite Loop Mode (CL) functional modes.
(2) Pins specified as CL should only be used when operating in Composite Loop Mode and left floating when operating in Buffer Mode.
(3) VSO and VS should be tied to the same potential since they are internally connected to each other through back-to-back diodes.
(4) I = input, O= output, P= power, NC = no connect.