JAJSMA5C June   2021  – March 2022 BUF802

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 説明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: Wide Bandwidth Mode
    6. 6.6 Electrical Characteristics: Low Quiescent Current Mode
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input and Output Over-Voltage Clamp
      2. 8.3.2 Adjustable Quiescent Current
      3. 8.3.3 ESD Structure
    4. 8.4 Device Functional Modes
      1. 8.4.1 Buffer Mode (BF Mode)
      2. 8.4.2 Composite Loop Mode (CL Mode)
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Oscilloscope Front-End Amplifier Design
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Transforming a Wide-Bandwidth, 50 Ω Input Signal Chain to High-Input Impedance
        1. 9.2.2.1 Detailed Design Results
        2. 9.2.2.2 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Layout Guidelines

Achieving optimum performance with the BUF802 requires careful attention to board layout, parasitics, and passive component selection. Consider the following:

  • Peaking in the S21 transfer function: keeping the trace length minimum is of prime importance to ensure no peaking occurs in the S21 transfer function of the BUF802. The trace inductance can form a resonant circuit with the input capacitance of the BUF802, causing peaking in the S21 response. Add a small resistor (R5 in Figure 11-1) in series with the DC blocking capacitor to dampen the LC resonance created by the trace inductance and the input capacitance of the BUF802. Choose series capacitors (C7 in Figure 11-1) with low equivalent series inductance (ESL) to minimize total inductance.
  • Power-supply bypass capacitors: mount the power-supply bypass capacitors as close to the supply pins as possible and on the same side of the PCB as the BUF802. As shown in Figure 11-1, choose low-inductance LICC capacitors (C5, C6, C13, and C10) to minimize high frequency impedance between the BUF802 and the bypass capacitors. Use multiple vias between the bypass capacitor and GND to reduce series inductance. As shown in Figure 11-1, also use multiple vias to GND on the 50 Ω input termination resistor (R3). Connect the bypass and termination vias to a solid GND plane.
  • High precision signal path, consisting of the precision op amp along with discrete components, can be adjusted and moved around to give precedence to the above two points. In the Figure 11-3, the precision components were placed on the opposite side of the PCB as the BUF802.
  • Thermal pad of the BUF802 is thermally conductive but electrically insulated to the die. This gives the circuit designer flexibility in connecting the thermal pad to any voltage. Choose a power or GND plane with the highest thermal mass for effective heat dissipation.